pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 146

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
PWM Polarity Register (PWMPOL)
This register controls the polarity of PWM0 to PWM7. The register is cleared (00
Location: 00 FD04
Type:
PWM Control Register (PWMCNT)
This register controls PWM operation. The register is cleared (00
Location: 00 FD06
Type:
Bit
Name
Reset
Bit
Name
Reset
3-1
7-5
Bit
7-0
Bit
0
4
Inverse PWM Outputs. Each bit controls the corresponding polarity of PWM0 to PWM7; e.g., INVP0 controls
PWM0.
0: The number in DCRi indicates for how many clocks (of down-counter decrements) the PWMi signal is high (de-
1: The number in DCRi indicates for how many clocks (of down-counter decrements) the PWMi signal is low
PWR (Power Mode). This bit controls the operating mode of the PWM, as follows:
0: Low Power mode. PWM input clock is disabled (stopped). Its registers are accessible and maintained. PWMi
1: Normal Power mode. PWM module is enabled. Its registers are accessible and its clock is functional.
Reserved.
PWMRES (PWM Resolution). This bit selects PWM 8-bit or 16-bit resolution.
0: 8-bit resolution. The clock pre-scaler divider is defined by bits 7-0 of PRSC register. The down-counter restarts
1: 16-bit resolution. The clock pre-scaler divider is defined by bits 15-0 of PRSC register. The down-counter re-
Reserved.
R/W
R/W
fault)
signal is 0 when INVPi bit is 0. The PWMi signal is 1 when INVPi bit is 1 (default)
from bits 7-0 of CTR register. The duty cycle is defined by bits 7-0 of the DCRi registers (default).
starts from bits 15-0 of CTR register. The duty cycle is defined by bits 15-0 of the DCRi registers.
16
16
7
0
7
0
Reserved
6
0
6
0
5
0
5
0
(Continued)
PWMRES
Description
Description
146
4
0
4
0
INVP7-0
16
) on reset.
3
0
3
0
16
) on reset.
Reserved
2
0
2
0
1
0
1
0
PWR
0
0
0
0
Revision 1.2