pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 396

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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C. Booter Program
C.2
The boot sequence is as follows:
1. If the chip has valid ADC calibration values in the information block, the Booter uses them to calibrate the ADC module.
2. The Booter checks the firmware (EC BIOS) header signature. If the signature is valid (4A49
• Forced Update 1: (1 byte at offset 5) Reserved.
• Forced Update 2: (1 byte at offset 6) Reserved.
• Forced Update 3: (1 byte at offset 7) Reserved.
• FlashSize: (1 byte at offset 8) Reserved.
• Reserved: (1 byte at offset 9) Reserved. This byte should be programed to 00
• MCFG_DAT: (1 byte at offset 10) Bits 3,4 and 5 are copied into MCFG register (address FF10
• ZONE0CFG: (1 word at offset 11) The Zone 0 configuration register value.
• ZONE1CFG: (1 word at offset 13) The Zone 1 configuration register value.
• XOR Checksum Result: (1 byte at offset 15)
• Protection Word (1 word at offset 16): Protection Word value.
• ZONE2CFG (1 word at offset 18): The Zone 2 configuration register value.
• PNMR (1 byte at offset 20): If this byte is different from FF
• Reserved: (3 bytes at offset 21
To verify the Header 2 checksum is correct, calculate the checksum starting at offset 00 of Header 2, up to the offset of
the “last_ROM_byte”, byte per byte; the resulting value must be 00
ister (address FBFE
Note: The Booter sets the BIU configuration registers before performing the checksum.
The XOR checksum result of Header 2, not including the checksum field at offset 4.
To generate the value of this field, first calculate the XOR checksum starting at offset 00 of Header 2, up to the offset of
the “last_ROM_byte”, not including offset 04 (Checksum) and offset 15 (XOR Checksum Result), byte per byte; then
store this number in offset 15 (XOR Checksum Result). The offset of the “last_ROM_byte” is the value of the ROM Size
minus 1.
To verify the Header 2 XOR checksum is correct, calculate the XOR checksum starting at offset 00 of Header 2, up to
the offset of the “last_ROM_byte”, not including offset 04 (Checksum), byte per byte; the resulting value must be 00
Note: The XOR Checksum Result value is counted in the normal Checksum operation; therefore, calculate the XOR
checksum before starting to calculate the normal Checksum (at offset 04).
If this word is different from 00
The lower byte is copied to PTWRL (address FF06
(address FF0A
This field is reserved. Set all 3 bytes to 00
Otherwise, it sets the ADC Calibration registers to the default values as follows:
Calibration Register Index
configures the BIU and other system settings, as specified by the header, as follows:
a. It sets MCFG register (Offset FF10
b. It sets MCFGSH register (Offset FBFE
c. In OBD mode only, It sets DBGCFG register (Offset FF16
d. It sets SZCFG0 register (Offset F984
e. It sets SZCFG1 register (Offset F986
f. It sets SZCFG2 register (Offset F988
g. It sets the High Frequency clock to the frequency specified in the Config field in Header 1. The accelerator clock is
If this word is 00
BOOT SEQUENCE
Width field in the Header is set to 16-bit mode. Bits 3,4 and 5 from MCFG_DAT field in Header 2 are copied to the
MCFG register.
disabled.
Value (Hex)
16
16
), bit 7 is not copied.
, the value of PTWRL and PTWRH registers is not changed.
16
).
(Continued)
16
AC
, its value is copied into PTWRL and PTWRH register as follows:
1
16
30
16
2
) bits 0 and 1 to enable expansion I/O and memory. Bit 2 is also set if the Bus
16
16
16
16
16
) to the value specified in ZONE0CFG field in Header 2.
) to the value specified in ZONE1CFG field in Header 2.
) to the value specified in ZONE2CFG field in Header 2.
16
) to the same value as MCFG.
30
.
3
16
16
F5
) and the higher byte to PTWRH (address FF08
4
16
396
F5
16
5
16
16
and bit 7 is set the value is copied into PNMR register
) bit 0, to enable an ISE interrupt.
00
16
6
16
.
00
7
16
87
16
8
16
.
87
9
16
88
10
16
16
16
or 4E49
) and MCFGSH reg-
85
11
16
16
).
16
8C
), the Booter
12
16
Revision 1.2
86
13
16
16
.