pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 120

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Quasi-Bidirectional Drivers
The quasi-bidirectional drivers have an open-drain output (Q2), an internal pull-up (Q3) and a low-impedance pull-up(Q1).
Q2 pulls the signal low whenever the output buffer data is ‘0’. The weak pull-up (Q3) is active whenever the output buffer
data is ‘1’ and WPUEN in PSCON register is set (1). The low impedance pull-up is active whenever the PC87591L-N05
changes the output data buffer from ‘0’ to ‘1’, thereby reducing the low-to-high transition time. The length of time that the
low-impedance pull-up is active is determined by HDRV field in PSCON register. A schematic description of this output driver
appears in Figure 38.
Interrupt Signals
The firmware can use an interrupt-driven scheme to implement the PS/2 device interface. When the shift mechanism is not
in use, four interrupts are available (PSINT4-1), one for each channel. (PSINT4 is not connected to the ICU as a separate
input, the MIWU PSCLK4 input should be used instead). When the shift mechanism is in use, only one interrupt signal is
used (PSINT1). More details on the use of the interrupts are provided in Section 4.6.4 on page 121. Figure 39 shows the
interrupt scheme with the associated enable bits.
Power Modes
The PS/2 interface is active only when the PC87591L-N05 is in Active mode. The shift mechanism should be disabled before
entering Idle mode. In Idle mode, the state of output signals cannot be changed (i.e., the firmware cannot write to PSOSIG
register, and the shift mechanism does not function).
When the PC87591L-N05 needs to wake up on a Start bit detection by the MIWU, the PS/2 channels that may serve as
wake-up event sources must be enabled before entering Idle mode. To enable them, set to 1 their corresponding CLK bits
in PSOSIG register.
The MIWU module can be used to identify a start bit in Idle mode and to return the PC87591L-N05 to Active mode. The
MIWU receives PSCLK4-1 and PSDAT4-1 signals as inputs (see Table 16 on page 103). The MIWU should be programed
to identify a falling edge on the clock or data lines of the enabled channels. In this configuration, a start bit causes the
PC87591L-N05 to switch from Idle mode to Active mode. Once Active mode is reached, the firmware should cancel the
transaction just started and then enable re-transmission of the information by the device.
Input Buffer Data
Output Buffer Data
SOT bit (PSTAT)
EOT bit (PSTAT)
DSMIE bit (PSIEN)
EOTIE bit (PSIEN)
SOTIE bit (PSIEN)
PSCLK4
PSCLK1
PSCLK2
PSCLK3
Figure 39. PS/2 Interface Interrupt Signals
Figure 38. Quasi-Bidirectional Buffer
Rising Edge
Detector
(Continued)
120
WPUEN
* Use PSCLK4 in the MIWU.
PSINT1
PSINT2
PSINT4*
PSINT3
Q1
Q2
+V
Q3
CC
Revision 1.2