pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 313

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
6.0 Host-Controlled Modules and Host Interface
Shared Memory Base Address High Byte Register
This register describes the high byte for the user-defined memory zone mapped to the shared memory (decoded as bits 31
to 24 of the 32-bit address range, bits 15-0 are 0). This register is reset to 00
Location: Index F5
Type:
Shared Memory Base Address Low Byte Register
This register describes the low byte for the user-defined memory zone mapped to the shared memory (decoded as bits 23
to 16 of the 32-bit address range, bits 15-0 are 0). This register is reset to 00
Location: Index F6
Type:
Bit
Name
Reset
Bit
Name
Reset
7-4
Bit
7-0
7-0
Bit
Bit
1
2
3
BIOS Extended Space Enable. Expands the BIOS address space to which the PC87591L-N05 responds to
include the Extended BIOS address range.
0: Disabled (default)
1: Enabled
User-Defined Memory Space Enable. When set, enables the PC87591L-N05 to respond to LPC memory read
and write accesses in the user-defined memory area range. The base address and size of the user-defined
range are specified by the Shared Memory Base Address High and Low Byte registers and the Shared Memory
Size Configuration register.
0: Disabled (default)
1: Enabled
BIOS FWH Enable. When set, enables PC87591L-N05 response to LPC-FWH transactions to the BIOS-FWH
space. The reset value of this register is defined by the SHBM configuration input. The value of this bit is later
updated based on the detected host BIOS scheme; see “Memory Range Programing” on page 311 for details.
0: Disabled (default when SHBM disable BIOS configuration)
1: Enabled (default when SHBM enable BIOS configuration)
BIOS FWH ID. These four bits correspond to the identification nibble, which is part of a FWH transaction (see
Section 6.1.7 for details).
User-Defined Memory Zone Address High. Defines the higher eight bits of the user-defined memory block
base address. The base address should be aligned on the selected block size.
User-Defined Memory Zone Address Low. Defines the lower eight bits of the user-defined memory block base
address. The base address should be aligned on the selected block size.
R/W
R/W
16
16
7
0
7
0
6
0
6
0
User-Defined Memory Zone Address High
User-Defined Memory Zone Address Low
5
0
5
0
Description
Description
Description
313
4
0
4
0
(Continued)
3
0
3
0
16
16
on Host Domain Hardware reset.
on Host Domain Hardware reset.
2
0
2
0
1
0
1
0
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0
0
0
0