pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 155

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Baud Rate Divisor Register (UnBAUD)
This byte-wide read/write register contains the lower eight bits of the baud rate divisor. The UnPSR register contains the
upper three bits. The register is cleared (00
Location: USART1 - 00 FD2C
Type:
Frame Select Register (UnFRS)
This byte-wide read/write register controls the selection of the frame format, including number of data bits, number of stop
bits and parity. The register is cleared (00
Location: USART1 - 00 FD28
Type:
Bit
Name
Reset
Bit
Name
Reset
1-0
5-4
Bit
2
3
6
7
CHAR. Selects the number of data bits per frame. Note that the parity bit is not included in the number of data bits.
Bits
1 0
0 0:
0 1:
1 0:
1 1:
STP. Programs the number of stop bits to be transmitted.
0: One stop bit transmitted (default)
1: Two stop bits transmitted
XB9. Contains the value of the 9th data bit for transmission only. The bit has no effect while operating with seven
or eight data bits per frame.
0: Transmit 0 as 9th data bit (default)
1: Transmit 1 as 9th data bit
PSEL. Controls the mode of parity bit generation and checking. Note that while operating with nine data bits-
per-frame, the parity bit is omitted. In this case, the value of PSEL has no effect.
Bits
5 4
0 0:
0 1:
1 0:
1 1:
PEN. Enables or disables the generation of a parity bit generation and parity check. Note that there is no parity
bit while operating in the nine data bits-per-frame mode. In this case, this bit has no effect.
0: Parity disabled (default)
1: Parity enabled
Reserved.
USART2 - 00 FC2C
R/W
USART2 - 00 FC28
R/W
Reserved
Description
Frame contains eight data bits (default)
Frame contains seven data bits
Frame contains nine data bits
Loopback mode selected; frame contains nine data bits.
Description
Odd parity (default)
Even parity
Mark (1)
Space (0)
7
0
7
0
16
16
16
16
PEN
6
0
6
0
16
16
) on reset.
) on reset.
5
0
5
0
(Continued)
PSEL
UDIV[7]: UDIV[0]
Description
155
4
0
4
0
XB9
3
0
3
0
STP
2
0
2
0
1
0
1
0
CHAR
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0
0
0
0