pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 145
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pc87591l-n05
Manufacturer Part Number
pc87591l-n05
Description
Lpc Mobile Embedded Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L-N05.pdf
(401 pages)
- Current page: 145 of 401
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Revision 1.2
4.0 Embedded Controller Modules
Cycle Time Register (CTR)
The CTR register controls the cycle time and duty cycle steps, CTR is set (FFFF
Location: 00 FD02
Type:
Duty Cycle Registers 0 to 7 (DCRi)
The DCRi (i = 0 to 7) registers control the duty cycle of PWMi output signal. DCRi is cleared (0000
Location: Channel 0 - 00 FD08
Type:
Bit
Name
Reset
Bit
Name
Reset
15-0 Cycle Time Value. The 8/16-bit down-counter divides the pre-scaler output clock either by CTR15-0 + 1 when
15-0 Duty Cycle Value. DCRi register defines the number of clocks for which PWMi is high (from the full cycle of the
Bit
Bit
PWMRES bit (in PWMCNT register) is set to 1, or by CTR7-0 + 1 when PWMRES bit is set to 0. For example,
a value of 0000
When PWMRES bit is set to 0, only the low byte (CTR7-0) of this register must be written (CTR15-8 are
ignored).
The contents of this register may be changed only when the PWM module is in Low Power mode. Otherwise,
there may be unpredictable results.
PWMi cycle), when Inverse PWMi bit in PWM Polarity register is 0.
If the DCRi value > CTR value, PWMi signal is always low.
If DCRi value == CTR value, PWMi signal is always high.
When Inverse PWMi bit is 1, the value of PWMi is inverse.
When PWMRES bit is set to 0, only the low byte (DCRi7-0) of this register must be written (DCRi15-8 are ignored).
R/W
Channel 1 - 00 FD0A
Channel 2 - 00 FD0C
Channel 3 - 00 FD0E
Channel 4 - 00 FD10
Channel 5 - 00 FD12
Channel 6 - 00 FD14
Channel 7 - 00 FD16
R/W
15
15
1
0
16
14
14
1
0
16
results in a divide by 1, a value of FFFF
13
13
1
0
16
16
16
16
16
16
16
16
12
12
1
0
11
11
1
0
(Continued)
10
10
1
0
9
1
9
0
Description
Description
145
DCRi15-0
CTR15-0
8
1
8
0
16
7
1
7
0
results in a divide by 65536.
6
1
6
0
16
) on reset.
5
1
5
0
4
1
4
0
3
1
3
0
16
) on reset.
2
1
2
0
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1
1
0
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