pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 42

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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2.0 Signal/Pin Description and Configuration
2.2.7
CLKRUN
GA20
KBRST
LAD0-3
LCLK
ECSCI
LDRQ
LFRAME
LPCPD
RESET1
RESET2
IOPC0
IOPE7-0
Signal
Signal
Host Interface
25
5
6
15-13, 10
18
31
8
9
24
19
30/165
168
25-24, 44,
2, 90-87
Pin(s)
LQFP
Pin(s)
LQFP
J4
C2
D1
D2, E2, F1,
F3
G1
J1
E4
E1
H2
G3
L3 (D5)
A6
J4, H2,
P1, B2,
P14, R15,
R14, P13
Ball(s)
FBGA
Ball(s)
FBGA
I/O
I/O IN
I/O IN
I/O
O
O
O
O
O
I
I
I
I
I
I
Buffer
Buffer
PCI
PCI
Type
IN
O
IN
IN
IN
Type
O
IN
IN
O
O
O
2/12
PCI
3/6
1/2
1/2
PCI
PCI
PCI
PCI
/O
CS
TS
/OD
PCI
6
Power
Power
Well
Well
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
CC
CC
DD
DD
CC
DD
DD
CC
CC
DD
CC
CC
42
General-Purpose Output Port IOPC0. IOPC0 is are
targeted for use as power supply control for the power
supply unit. It is accessible by the core for write and
configuration. On V
TRI-STATE; it is not affected by other types of reset.
General-Purpose Input Port. These pins serve as input-
only pins. The GPIO registers are accessible by the core
for read and configuration. The pins may be used as
GPIO or assigned to their respective alternate functions.
IOPE3-0 and IOPE5 do not have an internal pull-up
resistor option. Note that IOPE3-0 and IOPE7-6 are not
5V tolerant. See Section 2.4 on page 49 for GPIO pin
assignment to alternate functions. See Section 4.5 on
page 110 for further details on the GPIO pins and their
functionality.
Clock Run. Same as PCI CLKRUN. When high, it
indicates that the LPC clock will be slowed down or
stopped. In this case, the PC87591L-N05 may pull it down
to request full speed of the clock.
Gate A20. Implemented using IOPB5 port output. See
Section 5.5.4 on page 284 for signal operation and
behavior when V
Keyboard Reset Output. See Section 5.5.4 on
page 284 for signal operation and behavior when V
off.
LPC Address-Data. Multiplexed command, address
bidirectional data and cycle status.
LPC Clock. Practically the PCI clock (up to 33 MHz).
EC SCI. Generates an Embedded Controller SCI interrupt
to the chipset. This signal is typically connected to one of
the chipset GPI inputs.
LPC DMA Request. Encoded Bus Master request for
LPC I/F.
LPC Frame. Low pulse indicates the beginning of a new
LPC cycle or the termination of a broken cycle.
Power Down. Indicates that power will be shut off on the
LPC interface.
Reset 1. A falling edge on this signal starts a reset
sequence of the PC87591L-N05. For details, see
Section 3.2 on page 61.
Reset 2. A level low reset to the LPC interface and Host
Controlled Function configuration registers and Shared
Memory host registers. RESET2 is either assigned to one
of two optional pins or it is disabled. For details, see
Section 3.2 on page 61.
(Continued)
DD
CC
is off.
Power-Up reset, the default state is
Description
Description
Revision 1.2
DD
is