pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 172

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
ADC Configuration Register (ADCCNF)
This register controls the operation and global configuration of the ADC module. ADCCNF is cleared (00
Location: 00 FF22
Type:
ADC Clock Control Register (ACLKCTL)
This register controls the system clock to ADC clock division. ACLKCTL is set to 3F
Location: 00 FF24
Type:
ADC Delay Control Register (ADLYCTL)
This register controls the delay between “input switching” and “conversion start” for the voltage and temperature channels.
ADLYCTL is set to A7
Location: 00 FF26
Type:
Bit
Name
Reset
Bit
Name
Reset
Bit
Name
Reset
Must be
7-3 Reserved.
Bit
5-0
7-6
Bit
0
1
2
ADCEN (ADC Module Enable). Controls the operation of the ADC to minimize power consumption and prevent
glitch effects during configuration changes; see “Enabling and Disabling the ADC” on page 169.
0: ADC disabled (default)
1: ADC enabled
Reserved.
INTECEN (Interrupt from End-of-Cycle Event Enable). Enables generation of an ADC interrupt on an End-of
ADC-cycle event (EOCEV in ADCSTS register).
0: Disabled (default)
1: Enabled - ADC Interrupt from EOCEV
SCLKDIV (System Clock Division Factor). Used to divide the system clock in order to obtain the ADC clock.
The system clock frequency is set separately (see Figure 74 on page 212). The resulting ADC clock frequency
should be equal to 0.5 MHz.
Range: 4 to 63 (default is 63, decimal values); values 0 to 3 are illegal and may result in undetermined ADC behavior.
Reserved.
R/W
R/W
R/W
16
16
16
7
0
7
0
7
1
0
16
Reserved
on reset.
6
0
6
0
6
0
0
Reserved
Reserved
5
0
5
1
5
1
0
(Continued)
Description
Description
172
4
0
4
1
4
0
1
3
0
3
1
3
0
0
SCLKDIV
16
INTECEN
on reset.
2
0
2
1
2
1
X
Reserved
VOLDLY
X
1
0
1
1
1
1
16
) on reset.
ADCEN
X
0
0
0
1
0
1
Revision 1.2