pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 14

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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Table of Contents
4.18
4.19
4.17.4
4.17.5
HIGH-FREQUENCY CLOCK GENERATOR (HFCG) ............................................................. 212
4.18.1
4.18.2
4.18.3
4.18.4
4.18.5
4.18.6
4.18.7
THE DEBUGGER INTERFACE ............................................................................................... 221
4.19.1
4.19.2
4.19.3
4.19.4
4.19.5
4.19.6
4.19.7
The Power Management Controller Status Register (PMCSR) ................................. 210
Usage Hints ............................................................................................................... 211
Features .................................................................................................................... 212
Functional Description ............................................................................................... 212
HFCG States ............................................................................................................. 213
The Programmable Pre-Scaler: Core Domain Clock Generation .............................. 215
State Transitions ........................................................................................................ 215
48 MHz Clock Monitor ............................................................................................... 216
Features .................................................................................................................... 221
Structure .................................................................................................................... 221
Debugger Interface Functional Description ............................................................... 222
Test Access Port (TAP) ............................................................................................. 224
TAP Instruction Register ............................................................................................ 227
TAP Data Registers, Debugger Interface .................................................................. 229
Core Registers, Debugger Interface .......................................................................... 231
HFCG Registers ....................................................................................................... 216
(Continued)
Increasing Activity ................................................................................................ 209
Power Mode Switch Protection ............................................................................ 210
PMC Enabled SuperI/O Disabled State ............................................................... 213
SuperI/O Enabled State ....................................................................................... 215
HFCG Register Map ............................................................................................. 216
HFCG Control Register 1 (HFCGCTRL1) ............................................................ 217
HFCGM Low Value Register (HFCGML) ............................................................. 218
HFCGM High Value Register (HFCGMH) ............................................................ 218
HFCGN Value Register (HFCGN) ........................................................................ 218
HFCGI Low Value Register (HFCGIL) ................................................................. 219
HFCGI High Value Register (HFCGIH) ................................................................ 219
HFCG Pre-Scaler Register (HFCGP) ................................................................... 219
HFCG Control Register 2 (HFCGCTRL2) ............................................................ 220
Rx Data Link ......................................................................................................... 222
Tx Data Link ......................................................................................................... 222
Debugger Reset Circuit ........................................................................................ 223
ISE Interrupt Control ............................................................................................. 223
Clock Synchronization .......................................................................................... 224
TAP Signals .......................................................................................................... 225
TAP Controller ...................................................................................................... 225
Design and Construction ...................................................................................... 227
Instructions ........................................................................................................... 228
Debugger Interface Instructions ........................................................................... 228
Bit Arrangement and Mapping .............................................................................. 229
Functionality in Various TAP Controller States .................................................... 229
Debug Bypass Register (BYPASS) ...................................................................... 230
Debug Data Register (DBGDATA) ....................................................................... 230
Debug Abort Mask Register (DBGMASKS) ......................................................... 230
Core Register Map ............................................................................................... 231
Debug Receive Data Registers 0, 2, 4, 6, 8, 10, 12 and 14 (DBGRXD0-14) ....... 231
Debug Receive Status Register (DBGRXST) ...................................................... 232
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Revision 1.2