pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 35

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

1.0 Introduction
(Continued)
Following the boot process, the Shared Memory configuration registers (see Section 6.1.11 on page 311) enable setting
memory sharing. The configuration setting includes defining the memory protocol in use (memory or FWH) and the address
range used in the host address space. The configuration registers allow the defaults set by the SHBM strap input to be over-
ridden; this enables using the shared memory for purposes other than system BIOS (e.g., PC87591L-N05 firmware update
and protected storage of information).
1.5.3
Core Access to Host Controlled Peripherals
The core may access host domain devices through the Core to Host Controlled Functions access bridge. The bridge em-
ploys an indirect mapping scheme.
There is only a single set of peripheral registers for host and core use. The bus arbitration guarantees that only one of the
two register accesses occurs at any given time, but this does not prevent problems that may be caused by conflicting write
transactions. When such a case is expected, the core lock mechanism may be used to protect access to one or more of the
devices. For security reasons, the lock may also be used to protect against host access to devices.
The core accesses a register by specifying the logical device and the offset of the register within the logical device. Note that
the configuration registers’ index and data registers are also handled as a logical device. The core triggers a read by writing
1 to the read start bit and waits for the bit to clear; it can then read the data from the data register. The core triggers a write
by performing a write operation to the data register.
Section 5.4 on page 275 provides details of the bridge and its operation.
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