pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 112

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Alternate Function
The PxALT controls the use of each of the port pins for GPIO or for the pin’s respective alternate function.
When PxALT bit is cleared (0):
When a bit in PxALT is set (1):
Port Direction
The Port Direction register (PxDIR) controls the direction of the port. If set (1), each bit in the register causes the correspond-
ing port signal to serve as an output port, thus enabling the output buffer.
When cleared, the port serves as an input port signal, thus putting the output buffer in TRI-STATE.
If the corresponding bit in PxWPU is set, it also enables the pull-up.
Data Output
The Data Output (PxDOUT) register holds the data to be driven onto the pin, when the respective pin is configured as GPIO
and its direction is set as output.
Data Input
The Data Input (PxDIN) register returns the current value/state of the pin. This register can always be read.
Open Drain
To use the GPIO pin as an inverting open-drain output buffer, the software should clear the corresponding bit in PxDOUT
register and then use PxDIR register to set the value to the port pin.
When the signal direction is set as output (1), a value of 0 is forced. When the direction is set for input (0), the signal is in
TRI-STATE and is not forced low.
The internal weak pull-up can pull the signal high when it is not forced low, by writing (1) to the corresponding bit of PxWPU.
Input Echo Function
Some of the Px pins can echo the value of an input pin. Figure 33 shows the modified structure of Px port pins that support the
echo function. The input echo function may be used when the Px pin is configured to operate as a General-Purpose output pin.
Table 7 on page 56 defines pairs of input ports (Pi) and output ports (Po), and the Echo Enable bit associated with each pair.
When the pair’s Echo Enable bit is set, and if Po is configured as output, the value from the input bit (Pi) is output to the
respective output port (Po). When the pair’s Echo Enable bit is cleared, and if Po is configured as output, the value in
PxDOUT is output to the respective output port.
• The corresponding pin is used as a GPIO pin.
• The output buffer is controlled by the Direction and Data Output registers.
• The input buffer is routed to the Data Input register.
• The pull-up is enabled when both the PxWPU is set and the device puts the output buffer in TRI-STATE.
• The corresponding pin is used for an alternate function (i.e., a signal from/to some other PC87591L-N05 module).
• The output buffer data and TRI-STATE are controlled by signals from the alternate module.
• The input buffer is always enabled when the alternate function is an input; therefore, to minimize current consump-
• The pull-up is enabled when PxWPU is set and the device puts the output buffer in TRI-STATE.
In this case, the input buffer is blocked, except when the buffer is actually being read.
tion, the signal should be held above V
CC
0.2 or below GND+0.2V.
(Continued)
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