pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 274

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
5.3.9
• Enable Access to the shared memory: Before any access may occur, the shared memory access must be enabled
• Access to the Host boot block must be enabled by the core after the memory access configuration is completed.
• At different stages of the expansion memory programing by the host, communication between the core and host is
15-0 OWPLA15-0 (Override Write Protect Low Addresses 15 through 0).
Bit
using the SIO Configuration registers (see Section 6.1.11 on page 311). To enable shared memory as a boot device,
the SHBM strap should be set appropriately (see Section 2.2.11 on page 45).
required. Various mechanisms may be used for this, one of which is the Shared Memory Semaphore mechanism.
This mechanism is tuned for host-initiated operations that use polling on the registers. The core may receive an in-
terrupt or use polling to identify a semaphore change. An example of bit allocation is:
Bit 0 - Host requests control of expansion memory
Bit 4 - Core grants control to host
The sequence is:
1. Host sets bit 0 to request control of bus.
2. Core identifies that bit 0 is set and does the required operations, including setting HLOCK bit in
3. Core sets bit 4, indicating to the host that memory access is granted.
4. Host performs write/erase to the memory, as required.
5. Host clears bit 0, indicating completion of the process.
6. Core clears HLOCK and protects the memory.
7. Core indicates completion of process by clearing bit 4.
SMCCST register to enable host access.
Usage Hints
OWP15-2
OWP31-16
Each bit affects the host’s ability to write to one block. On the low addresses (covered by OWPLAi), the block
size is 8 Kbytes. For the other blocks it is 64 Kbytes. The block address is calculated as follows:
See Figure 93 on page 267 for a description of the block mapping. Bit 7 (OWPLA7) in SMCOWP0 register is
read only.
0: Do not override the host Write Protect setting for the block
1: Host writes for this block are disabled regardless of the setting of the respective bit in the host register
The following access limitations apply to the register’s bits:
Low Address Blocks, OWPLAi: from i*8K to (i+1)*8K 1
Other Blocks, OWPLj: from j*64K to (j+1)*64K
Core boot blocks that cover address 00 0000
Host boot blocks not in above group and ranging from (MBTA
All other blocks:
(Override Write Protect 15 through 2).
(Override Write Protect 15 through 0).
(Continued)
16
Description
274
to CR_Boot_Block_Size:
Host_Boot_Block_Size) to MBTA: RO
RO
RW
Revision 1.2