pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 65
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pc87591l-n05
Manufacturer Part Number
pc87591l-n05
Description
Lpc Mobile Embedded Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L-N05.pdf
(401 pages)
- Current page: 65 of 401
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Revision 1.2
3.0 Power, Reset and Clocks
In XOR-Tree mode, all PC87591L-N05 device pins are configured as inputs, except the last pin in the tree, which is the
XOR_OUT output. The buffer type of the input pins participating in the XOR-Tree is IN
of the buffer type of these pins in normal device operation mode (see Section 2.2 on page 38). The input pins are chained
through XOR gates, as shown in Figure 10. The power supply pins (AV
pins (AD9-0, DA3-0) and Crystal Oscillator pins (32KX1, 32KX2) are excluded from the XOR tree.
In the 176-pin LQFP package, the XOR-Tree chain starts with pin 69 (see Figure 10), continues with pins 70 (the next pin
in ascending order) through 176, goes to pin 1, and ends with XOR_OUT pin (68). In the 176-pin FBGA package, the XOR-
Tree chain starts with ball M9 (see Figure 10) and ends with ball P8. For a detailed description of the XOR-Tree chain for
both packages, see Table 11 on page 66. In the table, the chain direction is from top to bottom, and from left to right.
For correct XOR-Tree operation, all the XOR-Tree inputs must be set to a valid logic level (i.e., either below V
V
The maximum propagation delay through the XOR-Tree, from the start of the chain to the end of the chain (XOR_OUT) is
TBD.
Ball M9
IH
Pin 69
V
; see Section 7.2 on page 336).
SUP
Start of Chain
Ball N10
Pin 70
Figure 10. XOR-Tree Chain (Simplified Diagram)
Pin 176
Ball A2
(Continued)
65
Ball A1
Pin 1
CC
, V
CC
, V
DD
, V
Ball N9
T
Pin 67
(Input, TTL compatible), regardless
CORF
, V
BAT
, AGND, GND), Analog
Ball P8
Pin 68
End of Chain
XOR_OUT
IL
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