pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 2

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
Features
Embedded Controller System Features
Processing Unit
— CompactRISC CR16B 16-bit embedded RISC
— Up to 2 Mbytes address space
Internal Memory
— 4 Kbytes of ROM
— Boot block for CR16B
— Memory contents protection
— 4K of on-chip RAM
— All memory types can hold both code and data
Expansion Memory
— Up to 2 Mbytes of code and data
— Supports BIOS (flash) memory sharing with PC host
— Boot block for host code
— Hardware-protected boot zone with block protection
— Supports external memory power-down mode
— Field upgradable with flash or SRAM devices
— Supports host-controlled code download and
— Bus Interface Unit (BIU)
LPC System Interface
— Synchronous cycles, up to 33 MHz bus clock
— Serial IRQ
— I/O and memory read and write cycles
— Bootable memory support
— Reset input
— Base Address (BADDR) strap to determine the base
— LPCPD and CLKRUN support
— FWH Transaction support
Protection Function Support
— Memory access protection
Host Bus Interface (HBI)
— Comprises three host interface channels, which are
— Includes one, 8042 KBC-standard, interface (legacy
— Includes two PM interface ports (legacy 62
— Provides ACPI Embedded Controller with either
— Generates IRQ, SMI and SCI
— Provides IRQ1 and IRQ12 support
processor core (the “core”)
update
address of the Index-Data register pair
typically used for the KBC and ACPI Private or
Shared EC channels
60
and 68
Shared or Private interface through the PM interface
16
Three address zones for static devices (SRAM,
ROM, flash, I/O)
Configurable wait states and fast-read, single
cycle bus cycles
8- or 16-bit wide bus
, 64
16
16
, 6C
)
16
)
16
, 66
16
2
— Provides Fast Gate A20 and Fast Host Reset via
Interrupt Control Unit (ICU)
— 31 maskable vectored interrupts (of which 26 are
— General-purpose external interrupt inputs through
— Enable and pending indication for each interrupt
— Non-maskable interrupt input
Multi-Input Wake-Up (MIWU)
— Supports up to 32 wake-up or interrupt inputs
— Generates
— Generates interrupts to ICU
— Provides user-selectable trigger conditions
General-Purpose I/O (GPIO)
— 92 port pins.
— I/O pins individually configured as input or output
— Configurable internal pull-up resistors
— Special ports for internal keyboard matrix scanning
— Input for system On/Off switch
— 17 external wake-up events
— Low-cost external GPIO expansion through the
PS/2 Interface
— Supports four external ports: Keyboard, mouse and
— Supports
Four ACCESS.bus (ACB) Interface modules. Each
module:
— Is Intel SMBus
— Is ACCESS.bus master and slave
— Detects up to three simultaneous slave addresses
— Supports polling and interrupt controlled operation
— Generates a wake-up signal on detection of a Start
— Has an optional internal pull-up on SDA and SCL
Two Universal Synchronous/Asynchronous Receiver-
Transmitter (USART) modules
— A full-duplex USART channel
— Programmable baud rate
— Data transfer via interrupt or polling
— Synchronous mode with either internal or external
— 7-, 8- or 9-bit protocols.
firmware
external)
MIWU
Management Controller)
BIU I/O Expansion protocol
two additional pointing devices
accelerator
Condition while in Idle mode
pins
clock
16 open-collector outputs
Eight Schmitt inputs with internal pull-ups
byte-level
wake-up
®
and Philips I
event
handling
2
C
®
to
compatible
via
PMC
hardware
(Power
Revision 1.2