pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 87

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Indirect (Memory-to-Memory) Transfers
In Indirect (Memory-to-Memory) mode, data transfers use two consecutive bus cycles. The data is first read into a temporary
register and subsequently written into the destination. This mode is slower than Direct (Fly-By) mode, but it provides support
for different source and destination bus widths.
Indirect mode also facilitates block transfers between two memory elements. Each element is an addressed device and can
be either memory or an I/O device.
The appropriate DMA acknowledge signal for each channel is asserted during the Device B bus cycle.
If the bus policy is “intermittent”, maximum, throughput is every five clock cycles. If the bus policy is “continuous”, maximum
throughput is every two clock cycles on the internal core bus (otherwise, it uses four clock cycles).
When DIR bit is 0, the first bus cycle reads data from the source using the ADCAn counter, and the second bus cycle writes
the data into the destination using the ADCBn counter. When DIR bit is 1, the first bus cycle reads data from the source
using the ADCBn counter, and the second bus cycle writes the data into the destination using the ADCAn counter.
The number of bytes transferred in each cycle is taken from TCS bit in DMACNTLn register. After the data item has been
transferred, the BLTCn counter is decremented by one. The ADCAn and ADCBn counters are updated according to INCAn,
INCBn, ADA and ADB fields in DMACNTLn register.
Note:
For transfer operations between two memory areas, see “Software DMA Request” on page 90.
Bus State
CLK
DMRQi
ADDR
DMACKi
Bus State
CLK
DMRQi
ADDR
DMACKi
Figure 27. Indirect Bus Cycle (DIR=0)
Figure 28. Indirect Bus Cycle (DIR=1)
(Continued)
T1
T1
87
ADCB
ADCA
T2
T2
T1
T1
ADCA
ADCB
T2
T2
Tidle
Tidle
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