pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 307

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
6.0 Host-Controlled Modules and Host Interface
SuperI/O Configuration 5 Register (SIOCF5)
Location: Index 25
Type:
Bit
Name
Reset
3-2
5-4
7-6
3-0
7-5
Bit
Bit
0
1
4
Type
Type
R/W
R/W
R/W
R/W
R/W
WO
Reserved.
SMI to IRQ2 Enable. Enables using slot number 2 in the serial IRQ protocol as an SMI interrupt in
parallel to or instead of using the dedicated pin.
0: Disabled (default)
1: Enabled
Reserved.
SuperI/O Devices Enable. Controls the function enable of all PC87591L-N05 SuperI/O logical
devices, except shared memory and Mobile System Wake-Up Control (MSWC). This bit enables the
simultaneous disabling of these modules using a write to a single bit.
0: All SuperI/O logical devices in the PC87591L-N05 are disabled, except MSWC and shared memory
1: Each SuperI/O logical device is enabled according to its Activate register (Index 30
Software Reset. Read always returns 0.
0: Ignored (default)
1: Triggers the Host Domain Software Reset event, which resets the logical devices (see Section 6.1.3
Number of I/O Wait States.
Bits
3 2
0 0:
0 1:
1 0:
1 1:
Number of DMA Wait States.
Bits
5 4
0 0:
0 1:
1 0:
1 1:
Reserved.
16
7
0
on page 303)
Reserved
Number
0 (default)
2
6
12
Number
Reserved
2 (default)
6
12
6
0
5
0
SMI to IRQ2
Enable
307
4
0
Description
Description
(Continued)
3
0
2
0
Reserved
1
0
16
) (default)
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0
0