pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 128

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
4.0 Embedded Controller Modules
PS/2 Output Signal Register (PSOSIG)
The PSOSIG register is a byte-wide, read/write register. It allows setting the value of the PS/2 port signals. When the shift
mechanism is enabled, the clock control bits in this register define the active channel(s). On reset, this register is set to 47
Location: 00 FE86
Type:
Note: When CLK1, CLK2, CLK3 and CLK4 are all 0, this is interpreted as a shift mechanism reset. In this case, the
PS/2 Input Signal Register (PSISIG)
The PSISIG register is an 8-bit read-only register. It provides the current value of the PS/2 port signals.
Location: 00 FE88
Type:
Bit
Name
Reset
Bit
Name
Bit
0
1
2
3
4
5
6
7
PSTAT register and the shift state machine are reset to their initial state.
WDAT1 (Write Data Signal Channel 1). Controls the data output to channel 1 data signal (PSDAT1). Use of
this bit depends on whether or not the shift mechanism is enabled.
Note: WDAT1 is set by the hardware after the PC87591L-N05 detected a start bit (i.e., on entering Transmit Ac-
WDAT2 (Write Data Signal Channel 2). Controls the data output to channel 2 data signal (PSDAT2). For more
information, see the description of bit 1 (above).
WDAT3 (Write Data Signal Channel 3). Controls the data output to channel 3 data signal (PSDAT3). For more
information, see the description of bit 1 (above).
CLK1 (Enable Channel 1)
0: Forces the PSCLK1 pin low (0) and disables channel 0 of the shift mechanism.
1: Depends on whether or not the shift mechanism is enabled.
CLK2 (Enable Channel 2). Same as bit 3 of this register (described above) but for channel 2.
CLK3 (Enable Channel 3). Same as bit 3 of this register (described above) but for channel 3.
WDAT4 (Write Data Signal Channel 4). Controls the data output to channel 4 data signal (PSDAT4). For more
information, see the description of bit 1 (above).
CLK4 (Enable Channel 4). Same as bit 3 of this register (described above) but for channel 4.
R/W
RO
When the shift mechanism is disabled (EN bit in PSCON register is set to 0), the data in WDAT1 is output to
PSDAT1 signal.
When the shift mechanism is enabled (EN=1), WDAT1 should be set to 1, except when the shift mechanism is
in Transmit mode. In this case, when in transmit-inactive and it is intended to transmit data to channel 1, the
firmware should clear WDAT1 bit to force the transmit signaling (low) to the PS/2 device.
If WDAT1 is cleared (0), the output buffer data is 0 (i.e., PSDAT1 is forced low).
If WDAT1 is set (1), the output buffer data is 1 (i.e., PSDAT1 is pulled high by the internal pull-up and may
be pulled low by an external device).
tive state). If a transmission is aborted before Transmit Active state, WDAT1 should be set (1) prior to dis-
abling the channel.
When the shift mechanism is enabled (EN bit in PSCON register is set to 1), channel 1 of the PS/2 ports
is enabled.
When the shift mechanism is disabled (EN bit in PSCON register is set to 0), the clock line output buffer
data is 1 (i.e., the signal is pulled high by the pull-up, if enabled, and may be pulled low by an external de-
vice).
RCLK4
CLK4
16
16
7
0
7
WDAT4
RDAT4
6
1
6
RCLK3
CLK3
5
0
5
(Continued)
RCLK2
CLK2
Description
128
4
0
4
RCLK1
CLK1
3
0
3
WDAT3
RDAT3
2
1
2
WDAT2
RDAT2
1
1
1
WDAT1
RDAT1
0
1
0
Revision 1.2
16
.