pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 324
![no-image](/images/no-image-200.jpg)
pc87591l-n05
Manufacturer Part Number
pc87591l-n05
Description
Lpc Mobile Embedded Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L-N05.pdf
(401 pages)
- Current page: 324 of 401
- Download datasheet (2Mb)
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Host-Controlled Modules and Host Interface
The lockout condition is switched off immediately in the following situations:
6.2.12 Oscillator Activity
The RTC oscillator is active if:
The RTC oscillator is disabled in the following cases:
If the RTC oscillator becomes inactive, the following features are non-functional/disabled:
6.2.13 Interrupt Handling
The RTC has a single Interrupt Request line, which handles the following three interrupt conditions:
The interrupts are generated if the respective enable bits in CRB register are set prior to an interrupt event occurrence.
Reading the CRC register clears all interrupt flags. Therefore, when multiple interrupts are enabled, the interrupt service
routine should first read and store the CRC register and then handle all pending interrupts by referring to this stored status.
If an interrupt is not serviced before a second occurrence of the same interrupt condition, the second interrupt event is lost.
Figure 113 shows the interrupt timing in the RTC.
• If the Divider Chain Control bits, DV0-2, (bits 6-4 in CRA register) specify a normal operation mode (010
• When battery voltage is below V
• If bit 7 (VRT) of CRD register is 0, all input signals are enabled immediately on detection of system voltage above V
• V
• V
• During power-down (V
• The software wrote ‘00X’ to DV2-0 bits of CRA register. This disables the oscillator and, when V
• Timekeeping
• Periodic interrupt
• Alarm
• Periodic interrupt
• Alarm interrupt
• Update end interrupt
signals are enabled immediately on detection of system voltage above V
mediately on detection of system voltage above V
Fail state. In this case, the oscillator may stop oscillating and memory contents may be corrupted or lost.
decreases the power consumption from the battery connected to the V
CMOS RAM is not affected as long as the battery is present at a correct voltage level. Oscillation is resumed, either
by changing the DV2-0 bits, or after a V
CC
BAT
power supply is higher than V
power supply is higher than V
BAT
only), if the battery voltage drops below V
Flags (and IRQ) are reset at the conclusion of CRC read or by reset.
A = Update In Progress bit high before update occurs = 244 s
B = Periodic interrupt to update
C = Update to Alarm Interrupt = 30.5 s
P = Period is programed by RS3-0 of CRA
Bit 7
of CRA
Bit 4
of CRC
Bit 6
of CRC
Bit 5
of CRC
BATDCT
= Period (periodic int) / 2 + 244 s
CCON
BATMIN
Figure 113. Interrupt/Status Timing
, independent of the battery voltage, V
PP
and host domain hardware reset is active, all input signals are enabled im-
and V
Power-Up reset.
B
CC
244 s
CCON
P/2
is not present.
30.5 s
324
. This also initializes registers at offsets 00
P
(Continued)
A
C
BATMIN
P/2
CCON
BAT
, the PC87591L-N05 may enter Battery
pin. When disabling the oscillator, the
.
BAT
.
CC
16
is not present, it
through 0D
2
), all input
Revision 1.2
CCON
16
.
.
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