pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 253

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Modules
Host Interrupt Generation Modes
The Host Interface module generates three types of interrupts to the host: regular IRQ, SMI and SCI. The interrupt schemes
are designed to meet ACPI requirements for host interrupts. Two interrupt modes are supported: PC87570 Compatible and
Enhanced PM.
PC87570 Compatible Mode
PC87570 Compatible mode uses the same method for IRQ generation as the PC87570. It is available only for PM channel 1
and is enabled when EME in HIPMnCTL register is set to 0. Figure 89 shows this scheme.
The host configuration module assigns host interrupts to IRQ numbers (see Section 6.1.13 on page 317). IRQ11 is used as
an example interrupt and for the signal naming (the actual interrupt number used is determined by the IRQ routing logic).
When hardware-driven IRQ11 is disabled (PMHIE in HICTRL register is cleared), the firmware can control the IRQ11 signal
by writing to the signal’s respective bit in HIIRQC register. When hardware-driven IRQ11 is enabled (PMHIE is set to 1),
interrupts to the host are generated according to the status of the OBF flag.
In Normal Polarity mode (IRQNPOL in HIIRQC register is cleared), the PC87591L-N05 supports two types of interrupts: leg-
acy edge or legacy level. When an edge interrupt is selected (IRQM field in HIIRQC register is set to a value other than 0),
the interrupt signal default value is high (1). When an interrupt signal must be sent (i.e., OBF flag is set), a negative pulse is
generated. The pulse width is determined by the same field, IRQM, that selects the edge interrupt.
When a level interrupt is selected (IRQM in HIIRQC register is cleared), the interrupt signal is usually low (0). It is asserted
(1) to indicate that the respective OBF flag has been set. The signal is de-asserted (0) when the output buffer is read (i.e.,
OBF flag is cleared).
In Negative Polarity mode (IRQNPOL in HIIRQC register is set to 1), IRQ signal behavior is inverted from the behavior de-
scribed for normal polarity.
The PC87591L-N05 firmware can read the value of the IRQ11 signal by performing a read operation of IRQ11B bit in HIIRQC
register.
The core can also control the routing of interrupts generated by the PM channel to one of the following:
The core firmware should not enable more than one of these interrupts simultaneously. It should also update ST0 and ST1
bits to indicate the type of host interrupt used.
• IRQ signal, when IRQE bit in HIPMnIE register is set
• SMI output, when SMIE bit in HIPMnIE register is set
• SCI event, using the ECSCI output, when SCIE bit in HIPMnIE register is set.
IRQ11B bit (HIIRQC)
OBF
IRQM field (HIIRQ)
(Level or Edge)
Figure 88. IRQ, SCI and SMI Control in PC87570 Compatible Mode (PM Channel 1 Only)
Hardware
Interrupt
IRQ11B bit (HIIRQC)
(write)
IRQ11B bit (HIIRQC)
(read)
IRQNPOL bit (HIIRQC)
(Polarity)
1
0
(Hardware or Firmware)
PMHIE bit (HICTRL)
(Continued)
1
0
253
IRQE bit (HIPMnIE)
SMIE bit (HIPMnIE)
SCIE bit (HIPMnIE)
1
0
1
0
SCIPOL bit (HIPMnCTL)
SMIPOL bit (HIPMnIC)
(Part of SuperI/O
IRQ Routing
Configuration
and Polarity
Module)
SCI Source
SMI Source
Gathering
Gathering
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Serializer
IRQ
ECSCI
SMI