pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 242

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
This chapter describes functions that serve as an interface between the host and core domains. The functions are:
5.1
The PC87591L-N05 supports a standard Keyboard and Mouse Controller interface. This interface implements legacy ports
60
5.1.1
5.1.2
The PC87591L-N05 supports a keyboard/mouse communication channel that uses the standard command/status register
and data registers. It uses either polling- or interrupt-driven communication schemes with the host and/or core. The hard-
ware is designed to allow a race-free interface between the host and the PC87591L-N05.
The keyboard and mouse channel consists of three registers:
Host Addresses
The host processor accesses the PC87591L-N05 Keyboard/Mouse Host Interface registers at two addresses in the host ad-
dress space. These addresses are defined by two internal chip-select signals specified in the PC87591L-N05 host configu-
ration registers; see Section 6.1.10 on page 310). Legacy settings of these addresses are 60
status/command and data registers, respectively.
Table 32 describes the register mapping to the host processor I/O space. For simplicity, the Host Interface module specifi-
cation refers to the legacy addresses.
Core Interrupts
The Host Interface module generates four level (high) interrupts to the core ICU. These can be used by the firmware for
interrupt-driven control of the keyboard/mouse and/or PM channels.
Host Interrupts
The PC87591L-N05 Host Interface supports two interrupts to the host processor: Keyboard interrupt (legacy IRQ1) and
Mouse interrupt (legacy IRQ12). These interrupts may be controlled either by hardware, according to the host interface buff-
er status, or by the PC87591L-N05 firmware toggling the bit value.
• Keyboard and Mouse Controller Interface (legacy 60
• Two Power Management (PM) channels compliant with ACPI EC specifications; see Section 5.2 on page 251
• Shared Memory mechanism; see Section 5.3 on page 262
• Core Access to SuperI/O modules; see Section 5.4 on page 275
• Mobile System Wake-Up functions; see Section 5.5 on page 280
• Intel 8051SL-compatible Host interface
• Configured using two logical devices: Keyboard and Mouse
• DBBOUT - can be written by the core and read by the host processor.
• DBBIN - can be written by the host processor and read by the core.
• STATUS - can be read by both core and host processors. It has five bits (2, 4-7) that are written by the core. Three
Keyboard and
16
— 8042 KBD standard interface (ports 60
— Legacy IRQ: IRQ1 (KBD) and IRQ12 (mouse) support
— Fast Gate A20 and Fast Reset via firmware
other bits are controlled by the hardware to indicate the status of DBBIN and DBBOUT registers.
and 64
Mouse
Port
KEYBOARD AND MOUSE CONTROLLER INTERFACE
Features
General Description
16
.
Address
Legacy
Table 32. Mapping of the Host Interface Registers to the Host Processor
60
64
60
64
16
16
16
16
Keyboard/Mouse Command
Keyboard/Mouse Command
Keyboard/Mouse Data
Keyboard/Mouse Data
Internal Chip Select
16
, 64
16
)
16
, 64
242
16
); see Section 5.1
Write
Write
Read
Read
Type
Register Name
Command
Status
Data
Data
16
and 64
DBBIN (A2=0)
DBBIN (A2=1)
Mnemonic
DBBOUT
STATUS
16
for the
Revision 1.2