pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 189

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
If an address ARP or global match is detected:
1. The PC87591L-N05 asserts its SDAn pin during the acknowledge cycle.
2. MATCH in ACBnCST register, MATCHAF in ACBnST register (or GCMATCH if it is a global call address match, or ARP-
3. If INTEN in ACBnCTL1 register is set, an interrupt is generated if both INTEN and NMINTE in ACBnCTL1 register are set.
4. The software then reads XMIT in ACBnST register to identify the direction requested by the master device; it then clears
Slave Receive and Transmit
Slave Receive and Transmit are performed after a match is detected and the data transfer direction is identified. After a byte
transfer, the ACB module extends the acknowledge clock until the software reads or writes ACBnSDA register. The receive
and transmit sequences are identical to those used in the master routine.
Slave Bus Stall
When operating as a slave, the PC87591L-N05 stalls the ACCESS.bus by extending the first clock cycle of a transaction in
the following cases:
Slave Error Detection
The ACB detects illegal Start and Stop Conditions (occurring within the data transfer or the acknowledge cycle) on the AC-
CESS.bus. When an illegal Start or Stop Condition is detected, BER is set and MATCH and GMATCH are cleared, setting
the module as an unaddressed slave.
4.13.5 Power-Down
When the PC87591L-N05 is in Idle mode, the ACB module is not active, but retains its registers. An exception is the
ACBnCTL1 register, which is reset in Idle mode. If the ACB is enabled (ENABLE in ACBnCTL2 register is set) on detection
of a Start Condition, a wake-up signal is issued to the MIWU. This signal may be used to switch the PC87591L-N05 to Active
mode.
Following the Start Condition that woke up the PC87591L-N05, the ACB module can not check the address byte for a match.
The ACB responds with a negative acknowledge. The device should resend both the Start Condition and the address after
the PC87591L-N05 has had time to wake up.
Before entering Idle mode, make sure that BUSY in ACBnCST register is inactive. This guarantees that the PC87591L-N05
will not stop responding after it acknowledges an address that was sent.
4.13.6 SDA and SCL Pin Configuration
The SDAn and SCLn are open collector signals that the user can choose to enable or disable. SDAn and SCLn also have
internal pull-up resistors that the user may enable. For more information about configuring these pins, see Table 6 on
page 49 and Section 4.5.2 on page 111.
4.13.7 ACB Clock Frequency Configuration
The ACB module enables the user to set the ACCESS.bus clock frequency. The SCLn clock period is set by SCLFRQ in
ACBnCTL2 and ACBnCTL3 registers. This clock low period may be extended by stall periods initiated by the ACB module
or by another ACCESS.bus device. In case of a conflict with another bus master, a shorter clock high period may be forced
by the other bus master until the conflict is resolved.
• SDAST in ACBnST register is set.
• NMATCH in ACBnST register and NMINTE in ACBnCTL1 register are set.
MATCH if it is an ARP address) and NMATCH in ACBnST register are set. If XMIT in ACBnST register is set (i.e., Slave
Transmit mode), SDAST in the same register is also set to indicate that the buffer is empty.
NMATCH in the same register so that future byte transfers are identified as data bytes.
(Continued)
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