pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 195

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
ACB Control Register 2 (ACBnCTL2)
The ACBnCTL2 register enables/disables the module and determines the ACB clock rate. On reset and while the module is
disabled (ENABLE in ACBnCTL2 register is set to 0), ACBnCTL2 is cleared (00
Location: Channel 1 - 00 FF6A
Type:
ACB Control Register 3 (ACBnCTL3)
The ACBnCTL3 register expands the clock pre-scaler field and enables the match to ARP addresses. ACBnCTL2 is cleared
on reset (00
Location: Channel 1 -00 FF6E
Type:
Bit
Name
Reset
Bit
Name
Reset
7-1
1-0
7-3
Bit
Bit
0
2
ENABLE. When set, the ACB module is enabled. When the Enable bit is cleared, the ACB module is disabled,
ACBnCTL1, ACBnST and ACBnCST are cleared and the clocks are halted.
SCLFRQ6-0 (SCL Frequency bits 6 through 0). This field, together with SCLFRQ8-7 in ACBCTL3 register,
defines the SCL’s period (low time and high time) when the PC87591L-N05 serves as a bus master. The clock
low time and high time are defined as follows:
where t
SCLFRQ may be programed to values in the range of 00 0001000
outside this range gives unpredictable results.
SCLFRQ8-7 (SCL Frequency bits 8 and 7). Extends SCLFRQ field and is concatenated with bits 0-6, which
are part of ACBnCTL2 register. Detailed use of SCLFRQ is provided in the SCLFRQ6-0 description in
ACBnCTL2.
ARPMEN (ARP Match Enable). When set, enables the matching of an incoming address byte to the SMBus
ARP address (110 0001
address.
Reserved.
Channel 2 - 00 FFEA
Channel 3 - 00 FC4A
Channel 4 - 00 FC6A
R/W
Channel 2- 00 FFEE
Channel 3 - 00 FC4E
Channel 4 - 00 FC6E
R/W
16
).
t
t
SCL
SCLl
CLK
=4*SCLFRQ*t
= t
7
0
7
0
is the PC87591L-N05 clock cycle when in Active mode (see Section 7.6.3 on page 346).
SCLh
16
16
16
16
16
16
16
16
2
CLK
6
0
6
0
) while the ACB is in Slave mode. When cleared, the ACB does not respond to an ARP
Reserved
5
0
5
0
(Continued)
SCLFRQ6-0
Description
Description
195
4
0
4
0
3
0
3
0
2
(8
16
10
).
) through 11 1111111
ARPMEN
2
0
2
0
1
0
1
0
SCLFRQ8-7
2
(511
10
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ENABLE
). Values
0
0
0
0