pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 124

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
End of Receive
When the stop-bit is detected, the shift mechanism enters the “End-Of-Reception” state. In this state, the shift mechanism:
The shift mechanism stays in this state until it is reset.
Figure 41 shows the receive byte sequence, as defined by the PS/2 standard.
Transmit Mode
Transmit Inactive
When the shift mechanism is enabled and XMT bit in PSCON register is set (1):
Transmit Idle
The Transmit Idle state can be entered by setting the channel enable bit (CLK4-1 for channel 4-1, respectively). This enables
the channel to be used for transmission. In this state, the shift-mechanism sets the clock of the enabled channel high (1)
while the data line of that channel is held low and waits for a start bit. When a PS/2 device senses the clock signal high with
the data signal low, it identifies a transmit request from the PC87591L-N05.
The three channels not in use are disabled by forcing ‘0’ on their clock lines.
Start Bit Detection
The start bit is identified by a falling edge on the clock signal while the data signal is low (0).
When a start bit is detected, data transmission begins by outputting bit 0 (LSB) of the transmitted data and setting data bits
WDAT4-1 in PSOSIG register. This allows bit 0 of the transmitted data to be output on the PS/2 data signal (PSDAT1,
PSDAT2, PSDAT3 or PSDAT4, according to the active channel).
In addition, the hardware sets the SOT bit (to 1) and stores the active channel number in ACH field, indicating transmission
of the start bit in PSTAT register. Note that if SOTIE bit in PSIEN register is set, an interrupt signal to the ICU is set high.
The firmware can use this interrupt to start a time-out timer for the data transfer.
Transmit Active
After identifying the start bit, the shift mechanism enters the Transmit Active state. The clock signal of the selected device
(PSCLK1, PSCLK2, PSCLK3 or PSCLK4) sets the data bit rate.
After each of the next seven falling edges of the clock line, one more data bit (bits 1 through 7) is driven on the data line of
the active channel (either PSDAT1, PSDAT2, PSDAT3 or PSDAT4).
On the ninth falling edge of the clock, the parity bit is output. The parity bit is high (1) if the number of bits with a value of 1
in the transmitted data was even (i.e., odd parity).
The tenth falling edge causes a 1 to be output as a stop bit. The data signal remains high to allow the PS/2 device to send
the line control bit.
• Disables all the clock signals by forcing them low
• Sets End-Of-Transaction status bit (EOT = 1 in PSTAT register)
• If EOTIE bit in PSTAT register is set, it asserts (1) the interrupt signal to the ICU.
• The shift mechanism enters Transmit mode in Transmit Inactive state with all clock signals low and data signals high
• The firmware writes the data to be transmitted to the PS/2 data register (PSDAT).
• The data line of the channel to be transmitted is forced low by the firmware clearing its data bit (WDAT4-1 for chan-
(PSOSIG = 47
nels 4-1, respectively).
CLK
DATA
16
).
Start Bit
CLK
1st
Figure 41. PS/2 Receive Data Byte Timing
Bit 0
CLK
2nd
(Continued)
124
Parity Bit
10th
CLK
Stop Bit
CLK
11th
Revision 1.2