pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 133

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
In this mode of operation, timer/counter 2 can be used as a simple system timer, an external event counter or a pulse accu-
mulate counter. Counter TnCNT2 counts down with the clock selected via the counter 2 clock selector, and TnCNT2 can be
configured to generate an interrupt on underflow if the interrupt is enabled by TnDIEN bit. See Section 4.7.4 on page 136
for detailed information.
Mode 2, Dual Input Capture
Dual Input Capture mode can be used to precisely measure the frequency of an external clock that is slower than the se-
lected clock source frequency or to measure the elapsed time between external events. A transition received on the TAn or
TBn pin causes a transfer of timer/counter 1 contents to TnCRA or TnCRB register, respectively. In this mode, timer/counter
2 can be utilized as a system timer that is pre-loaded by software and generates an interrupt on underflow.
Figure 47 shows a block diagram of the timer operating in mode 2. In this mode of operation, the timebase of the capture
timer is formed by counter 1, which counts down with the clock selected via the counter 1 clock selector. In Dual Input Cap-
ture mode, TAn and TBn pins function as capture inputs. A transition received on TAn pin causes a transfer of the timer
contents to TnCRA register. Similarly, a transition received on the TBn pin causes a transfer of the timer contents to TnCRB
register. TAn and TBn inputs can be configured to perform a counter preset to FFFF
In this case, the current value of the counter is transferred to the corresponding capture register; following this, the counter
is preset to FFFF
while reducing CPU overhead.
The pulse width of the input signal on TAn and TBn must be equal to or greater than one system clock cycle (see
Section 7.6.10 on page 358 for additional details). The values captured in TnCRA register at different times reflect the
elapsed time between transitions on the TAn pin. The same is true for TnCRB register and the TBn pin. Each input pin can
be configured to sense either rising or falling edge transitions.
The timer can be configured to generate interrupts on reception of a transition on either TAn or TBn. The interrupts can be
enabled or disabled separately for TAn or TBn by TAnIEN and TnBIEN bits. An underflow of TnCNT1 can also generate an
interrupt if the interrupt was enabled by TnCIEN bit. All three interrupts have individual pending flags. See Section 4.7.4 on
page 136 for detailed information.
Timer/counter 2 can be used as a “simple” system timer in this mode of operation. The TnCNT2 counter counts down with
the clock selected via the counter 2 clock selector, and TnCNT2 can be configured to generate an interrupt on underflow if
the interrupt was enabled by TnDIEN bit. See Section 4.7.4 on page 136 for detailed information.
Note that TnCNT1 cannot operate in the “Pulse Accumulate” or “External Event Counter” modes of operation since TBn input
is used as a capture input. Selecting either “Pulse Accumulate” mode or “External Event Counter” mode for TnCNT1 causes
TnCNT1 to stop. However, all available clock source modes may be selected for TnCNT2. Thus it is possible to use TnCNT2
to determine the number of capture events on TBn or the elapsed time between capture events on TBn.
Timer 1
Timer 2
Selector
Clock
Clock
Clock
16
. Using this approach enables an external signal’s on-time, off-time or period to be directly determined,
Figure 46. Mode 1, PWM and Counter
Reload A = Time 1
Timer/Counter 1
Reload B = Time 2
Timer/Counter 2
TnCNT1
TnCRA
TnCNT2
TnCRB
(Continued)
Underflow
Underflow
133
Underflow
TDPND
TAPND
TBPND
16
TDIEN
TAIEN
TBIEN
TAEN
on reception of a valid capture event.
Interrupt 2
Interrupt 1
Interrupt 1
Timer
Timer
Timer
TAn
TBn
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