pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 169

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Enabling and Disabling the ADC
Enabling the ADC. The ADC is enabled by setting ADCEN in ADCCNF register to 1.
After the ADC is enabled, its internal circuits need an activation delay of 100 s. This activation delay should be added to
the ADC cycle until the first batch of measurements (after enabling the ADC) is available. Note that after activation, the first
set of results using the large scale mode (CSCALE bit in VCHiCTL register is clear) may be wrong.
Other measurement operations may be enabled or disabled individually. When measurement conversions are enabled while
the ADC is enabled, the measurement operations start on the following conversion cycle.
Disabling the ADC. The ADC is disabled by resetting ADCEN in ADCCNF register when one of these conditions applies:
In this state, all ADC activities are halted and ADC current consumption from the AV
ADC causes an activation delay.
It is recommended to disable the ADC only after the buffer registers of all four channels have been read.
Interrupt Structure
The ADC Interrupt is a level high interrupt, generated if one (or more) of the events in Table 21 becomes active. The ADC
interrupt is connected to the ICU.
When an event flag and its related mask bit are set (enabled), the ADC Interrupt request is asserted. This is indicated by
a high level of the ADC Interrupt signal.
The software must reset the event flag (or reset its mask bit) in order to deassert the ADC Interrupt request.
All the interrupt mask bits (interrupt disabled), the data-related event flags (EOCEV and the four DATVAL bits) are cleared
by both reset conditions.
The ADC Interrupt is routed to the ICU as an ADCI signal (see Section 4.3 on page 96).
ADC Operating Principles
Measurement Sequence. The following measurements are executed during one ADC cycle, for all enabled channels (in
the following order):
1. Calibration measurement.
2. Voltage measurement for Voltage Channel 1, from the input selected by SELIN field in VCHN1CTL register. The A/D
3. Voltage measurement for Voltage Channel 2, as above, using the VCHN2CTL and VCHN2DAT registers.
4. Voltage measurement for Voltage Channel 3, as above, using the VCHN3CTL and VCHN3DAT registers.
5. End of the ADC cycle. EOCEV bit in ADCSTS register is set (in addition to all the relevant DATVAL bits).
The software may read the measurement result for each channel immediately after its DATVAL bit is set. Alternatively, the
results may be read at the end of the cycle when EOCEV bit is set. After the data in VCHNiDAT register is read, the software
should clear the relevant DATVAL bit to indicate that the data in the buffers has been read.
The ADC cycle duration may be calculated using the formula below (N is the number of enabled voltage channels):
• V
• Warm reset
• Core enters Idle mode
• The software resets the ADCEN bit.
conversion starts by selecting the input and waiting for the time period (VOLDLY delay) set in ADLYCTL register. The
resulting 8-bit digital value is stored in VCHN1DAT register, and DATVAL bit in VCHN1CTL register is set. Note: This
measurement is skipped if Voltage Channel 1 is disabled by setting the SELIN field in VCHN1CTL register to 1F
CC
T
Event Flag
ADC cycle
DATVAL
DATVAL
DATVAL
Power-Up reset
EOCEV
= 42.2 ms + (N+1)
VCHN1CTL
VCHN2CTL
VCHN3CTL
Mnemonic
Register
ADCSTS
INTECEN
INTDVEN
INTDVEN
INTDVEN
Mask Bit
Table 21. ADC Interrupt Structure
*
(t
(Continued)
VCHN1CTL Data Valid Event/Enable (Voltage Channel 1)
VCHN2CTL Data Valid Event/Enable (Voltage Channel 2)
VCHN3CTL Data Valid Event/Enable (Voltage Channel 3)
Mnemonic
ADCCNF
Register
VD
+ t
169
VC
End-of-Cycle Event/Enable
)
CC
Description
is reduced. Note that re-enabling the
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