pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 84

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
4.0 Embedded Controller Modules
4.1.11 Usage Hints
The following usage hints help configure the BIU to maximize PC87591L-N05 performance and avoid contention on the data
bus.
1. Memory Sections 0 and 1 (fast zone) and Section 2 (slow zone) can use a fast read bus cycle through the operation
2. To avoid contention on the data bus when a read bus cycle (no T
15-12 Reserved.
Bit
10
11
frequency of the PC87591L-N05; therefore, program SZCFG1 fields to be: WAIT=000, HOLD=00, BRE=0, WBE=0,
BW=1, FRE=1.
When Section 2 (slow zone) can operate with a fast read bus cycle, program SZCFG2 fields to be: WAIT=000,
HOLD=00, BRE=0, WBE=0, BW=1, FRE=1.
When Section 2 (slow zone) needs to operate with normal read and zero wait, program SZCFG2 fields to be: WAIT=000,
HOLD=00, BRE=0, WBE=0, BW=1, FRE=0.
cycle in another zone, program IPST and IPRE in the different memory (I/O) zones as follows:
IPRE (Idle Before Bus Cycle). This bit inserts an idle cycle before the current bus cycle when this bus cycle is
in a new zone.
0: No idle cycle inserted
1: Idle cycle inserted (default)
FRE (Fast Read Enable).
0: Disabled - Normal read bus cycle takes at least two clock cycles (default)
1: Enabled - Normal read bus cycle takes one clock cycle
1. Set IPRE when the zone is configured for fast
2. An IPRE is forced always for zone I/O.
read.
Zone I/O
Zone 0
Zone 1
Zone 2
Zone
(Continued)
Description
IPRE
84
0/1
1
0
1
2
1
hold
IPST
clock cycles) in one zone is followed by a read bus
0
0
0
0
Revision 1.2