pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 397

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
C. Booter Program
3. If the USART configuration bit (Bit 1 in Config field in Header 1) is set, the Booter configures the USART1 module as
4. The Booter checks the validity of the firmware (EC BIOS) using code checksum.The sum operation begins at the starting
5. If the firmware (EC BIOS) is valid, the Booter jumps to the firmware (EC BIOS) entry point (also specified in the header).
Note: You can define memory writes for the Booter, so that it can perform writes to any type of flash module mapped in
C.3
The PC87591L-N05 Booter enters Recovery mode if any of the following EC Firmware problems occurs:
In Recovery mode, you can connect to the PC87591L-N05 and communicate with the internal monitor via JTAG or RS-232
debugging channels.
While the Booter is in Recovery mode, RAM resources from address F6A0
section while debugging.
C.3.1
If the RS-232 channel is used:
This connection needs a driver/receiver to transform the voltage between the host RS-232 ( 12V) and the PC87591L-N05
USART (3V).
The RS-232 channel settings must be:
Resources needed:
• The firmware (EC BIOS) signature is invalid.
• The firmware (EC BIOS) code checksum is wrong.
• Force recovery mode bit (bit 2) in Config field in Header 1 is set.
• The firmware (EC BIOS) is valid, an abort signal is sent via debugging channel at run-time and the EC-BIOS dispatch
• Connect IOPB0/URXD1 to the RS-232 RX pin.
• Connect IOPB1/UTXD1 to the RS-232 TX pin.
• 38400 bps baud rate.
• Software flow control.
• Software reset.
• Host system must have a serial port available.
• CR16B debugging tools must be installed.
h. It sets the PTWRL and PTWRH registers (Offset FF06
i.
j.
follows:
a. It sets PBALT register (Offset FE32
b. It sets PBWPU register (Offset FE30
c. It sets UPSR register (Offset FE2E
d. It sets UICTRL register (Offset FD24
e. It sets IENAM1 register (Offset FE10
address of Header 2 (as specified in Header 1), and includes the area of the firmware (EC BIOS) memory, as specified
in Header 2 (ROM-size field).
At this point, all resources (RAM) used by the Booter are free and available.
If the firmware (EC BIOS) is invalid, the Booter enters Recovery mode and acts as a Target Monitor (TMON), implementing
debugging functionality via JTAG or RS-232 debugging channels, as described in the TMON Communication Protocol.
table is initialized as described in Section C.6.
byte of the Protection Word field (in Header 2) respectively, if the field value is other than 00
16
It sets PNMR register (Offset FF0A
FF
ART transaction is received in Recovery mode).
the external memory.
RECOVERY MODE
RS-232 Connection
It clears HOSTWAIT bit (sticky bit) in MCFG register (Offset FBFE
16
and bit 7 is not set. Bit 7 is not copied.
(Continued)
16
16
16
16
16
16
) to C8
) to the value specified in PNMR field in Header 2 if the value is different from
) bit 1, to enable RX alternate function. (TX remain disabled until the first US-
) bit s1 and 2, to enable weak pull-up and to avoid noise interference.
) bit 6, to enable the RX interrupt.
) bit 0, to enable the USART1 interrupt in ICU module.
16
, to set up the baud rate.
397
16
and FF08
16
to F7FF
16
16
) to the value specified in the low byte and high
) to release the host from LPC wait state.
16
are used. Do not change data in this memory
16
.
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