pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 184

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
4.0 Embedded Controller Modules
4.13 ACCESS.BUS (ACB) INTERFACE
The PC87591L-N05 includes four SMBus/ACCESS.bus Interface (ACB) modules. The registers of each module are prefixed
with ACBn, and the signal names are suffixed with ‘n’, where ‘n’ is module number 1, 2, 3 or 4.
Each ACCESS.bus interface is a two-wire serial interface that is compatible with the ACCESS.bus physical layer. It is also
compatible with Intel’s SMBus and Philips’ I
maintain bidirectional communication with multiple master and slave devices. As a slave device, the ACB module may issue
a request to become the bus master.
The ACB interface provides full support for a two-wire ACCESS.bus synchronous serial interface. It permits easy interfacing
to a wide range of low-cost memories and I/O devices, including EEPROMs, SRAMs, timers, A/D converters, D/A convert-
ers, clock chips and peripheral drivers.
4.13.1 Features
4.13.2 Functional Description
The ACCESS.bus protocol uses a two-wire interface for bidirectional communication between the ICs connected to the bus.
The two interface lines are the Serial Data Line (SDLn) and the Serial Clock Line (SCLn). These lines should be connected
to a positive supply via a pull-up resistor and remain high even when the bus is idle.
The ACCESS.bus protocol supports multiple master and slave transmitters and receivers. Each IC has a unique address
and can operate as a transmitter or a receiver. Some peripherals are receivers only.
During data transactions, the master device initiates the transaction, generates the clock signal and terminates the transac-
tion. For example, when the ACB initiates a data transaction with an attached ACCESS.bus-compliant peripheral, the ACB
becomes the master. When the peripheral responds and transmits data to the ACB, their master/slave (data transaction ini-
tiator and clock generator) relationship is unchanged even though their transmitter/receiver functions are reversed.
Data Transactions
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCLn). Con-
sequently, throughout the clock’s high period, the data should remain stable (see Figure 66). Any change on the SDAn line
while SCLn is in high state during a transaction causes the current transaction to abort. New data should be sent during the
low SCLn state. This protocol permits a single data line to transfer both command/control information and data, using the
synchronous serial clock.
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condi-
tion to terminate the transaction. Each byte is transferred with the most significant bit first. An Acknowledge signal must fol-
low each byte (8 bits). The following sections provide further details of this process.
At each clock cycle, the slave can stall the master while it handles the previous data or prepares new data. The slave does
this, for each bit transferred or on a byte boundary, by holding SCLn low to extend the clock low period. Typically, slaves
extend the first clock cycle of a transfer if a byte read has not yet been stored or if the next byte to be transmitted is not yet
ready. Some microcontrollers with limited hardware support for the ACCESS.bus extend the access after each bit, thus al-
lowing the software time to handle this bit.
• ACCESS.bus, SMBus and I
• ACCESS.bus master
• ACCESS.bus slave
• Supports polling- interrupt- and DMA-controlled (n=3 and 4 only) operation
• Generates a wake-up signal on detection of a Start Condition in Power-Down mode
• Optional internal pull-up on SDAn and SCLn pins
— One or two user-defined addresses
— Global (broadcast) address
— ARP address
2
C compliant
SDAn
SCLn
2
C bus. The module can be configured as either a bus master or slave and can
Figure 66. Bit Transfer
Data Line
Stable:
Data Valid
(Continued)
184
Change
of Data
Allowed
Revision 1.2