pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 252

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
Data Registers
The PM channel has three registers.
Host Addresses
The host processor accesses the PC87591L-N05 PM channel interface registers at two addresses in the host address
space. These addresses are defined by two internal chip select signals specified in the PC87591L-N05 host configuration
registers; see Section 6.1.13 on page 317 and Section 6.1.14 for channels 1 and 2, respectively. The Legacy setting of these
addresses is 62
Table 33 shows the register mapping to the host processor I/O space. For simplicity, the Host Interface module specification
refers to the legacy addresses.
Core Interrupts
For each channel, the Host Interface module generates two level (high) interrupts to the core ICU (see Figure 87). The firm-
ware can use these for interrupt-driven control of the PM channels.
In PC87570 Compatible mode (EME in HIPMnCTL register is set to 0), interrupts are enabled using HICTRL register bits
PMOCIE and PMICIE for output buffer empty and input buffer full interrupts, respectively.
In Enhanced PM mode (EME in HIPMnCTL register is set to1), interrupts are enabled using HIPMnCTL register bits OBEIE
and IBFIE for output buffer empty and input buffer full interrupts, respectively.
• DBBOUT - can be written to by the core and read by the host processor. Multiple addresses in the core address
• DBBIN - can be written to by the host processor and read by the core.
• STATUS - can be read by both the core and the host processor. It has five bits (bits 2 and 4-7) that are written to by
Channel n
OBEIE bit (HIPMnCTL)
space enable generating an IRQ, SMI or SCI interrupt on Output Buffer Full (OBF).
the core directly or, in Enhanced PM mode, via the control and configuration register. Three other bits are controlled
by hardware to indicate the status of DBBIN and DBBOUT registers.
PMOCIE bit (HICTRL)
IBFIE bit (HIPMnCTL)
Port
1. The legacy address serves as an example only. Do not assign the same address for both channels.
PMICIE bit (HICTRL)
PM
Address
Legacy
16
62
66
62
66
EME bit (HIPMnCTL)
EME bit (HIPMnCTL)
and 66
16
16
16
16
OBF bit (HIPMnST)
IBF bit (HIPMnST)
1
16
Index 60
Index 62
Index 60
Index 62
Register Index
Table 33. Host Interface Registers to Host Processor Mapping
for channel 1 Status/Command and Data registers, respectively.
Configuration
1
1
0
0
16
16
16
16
Figure 87. Core Interrupt Request for PM Channel n
, 61
, 63
, 61
, 63
16
16
16
16
PM Internal Chip
Command/Status
Command/Status
(Continued)
Select
Data
Data
252
Type
Write
Write
Read
Read
PMnOBE
Interrupt
Interrupt
PMnIBF
Command
Register
Status
Name
Data
Data
Mnemonic
ICU
DBBOUT
STATUS
DBBIN
DBBIN
Revision 1.2