pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 311

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
6.0 Host-Controlled Modules and Host Interface
6.1.11 Shared Memory Configuration
Logical Device 15 (0F
Table 49 lists the configuration registers that affect the shared memory functional block. The shared memory base address
registers point to the shared memory registers described in Section 5.3 on page 262. The memory space to which the shared
memory responds is defined by the configuration registers in the following sections. See “Standard Logical Device Config-
uration Register Definitions” on page 299 and Section 6.1.2 on page 302 for a detailed description of the other configuration
registers.
Memory Range Programing
LPC memory transactions and/or LPC-FWH transactions can be forwarded to the PC87591L-N05 shared memory. The
Shared Memory Configuration register defines the transaction type and address range to which the PC87591L-N05 re-
sponds. The SHBM strap inputs affect the default settings of the Shared Memory Configuration register to enable boot pro-
cess from shared memories. Two memory areas may be individually enabled: a user-defined zone and BIOS memory (either
BIOS-LPC and/or BIOS-FWH spaces).
To enable BIOS support, set the SHBM strap inputs to select any of the BIOS modes (see Section 2.3 on page 48 for de-
tails). The PC87591L-N05 responds to LPC memory read and write transactions from/to the BIOS address spaces, shown
in Table 50, as long as BIOS LPC Enable (bit 0) of the Shared Memory Configuration register is set.
The PC87591L-N05 responds to LPC-FWH read and write transactions from/to the high memory address range (’386’ mode
BIOS range), shown in Table 50, as long as BIOS FWH Enable (bit 3) of the Shared Memory Configuration register is set.
30
60
61
70
71
74
75
F4
F5
F6
F7
Index
16
16
16
16
16
16
16
16
16
16
16
Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
Base Address MSB register.
Base Address LSB register. Bits 3-0 (for A3-A0) are read only, ‘0000’.
No interrupt assignment.
No interrupt assignment.
Report no DMA assignment.
Report no DMA assignment.
Shared Memory Configuration register.
Shared Memory Base Address High Byte register.
Shared Memory Base Address Low Byte register.
Shared Memory Size Configuration register.
000E 0000
000F 0000
FFE0 0000
Memory Address Range
16
16
16
16
) (Shared Memory) Configuration
- 000F FFFF
- 000E FFFF
- FFFF FFFF
Configuration Register or Action
Table 49. Shared Memory Configuration Registers
Table 50. BIOS-LPC Memory Space Definition
16
16
16
Extended BIOS range (Legacy); only when Extended
BIOS Enable bit in Shared Memory Range Configuration
register is set.
BIOS Range (Legacy)
386 mode BIOS range; this is the upper 2 Mbytes of the
memory space.
311
(Continued)
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
SHBM strap input
00
pending on the
16
value of the
or 09
Reset
00
00
00
00
00
04
04
00
00
00
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16
16
16
16
16
16
16
16
16
16
16
, de-