pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 62

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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3.0 Power, Reset and Clocks
Unless otherwise noted, reset references throughout the PC87591L-N05 modules default to the following types:
In DEV environment, the PC87591L-N05 outputs to the BRKL_RSTO signal an indication that a reset occurred at the core
domain. See Section 4.20.3 on page 236 for the implementation and usage of RSTO.
The following sections detail the sources and effects of the various resets on the PC87591L-N05, per reset type.
3.2.1
V
tects the status of the V
as “good” (i.e., V
For more details, see Section 6.2.9 on page 322.
3.2.2
V
er is applied. This reset is completed t
If the 32 KHz crystal is disabled before V
PC87591L-N05. Any host processor access during this time results in:
On V
3.2.3
The PC87591L-N05 generates a Watchdog reset on request from the TWD module (i.e., a watchdog signal is asserted). It
generates a Debugger Interface reset on request from the Debugger Interface module (reset command). During these re-
sets, the PC87591L-N05 performs the V
The reset periods are identical to the V
• For V
• For core domain functions and host-core interface functions: V
• For host domain functions: Host Domain reset
• The host processor is stalled (by driving a “Long WAIT sync” response on the LPC bus) until after the reset process
• If HRAPU bit in MSWCTL1 register is set (1), the host processor is reset by asserting KBRST until the internal reset
• Enables the 32 KHz crystal, if it is disabled.
• Resets the High-Frequency Clock Generator (HFCG) to its default frequency.
• Loads default values to all registers whose values are retained by V
• Puts pins with strap options into TRI-STATE and enables the internal pull-downs on the strap pins.
• Samples the values of the strap pins.
• Resets the TAP controller of the Debugger Interface module.
• Resets the MSWC, excluding those MSWC registers whose values are retained by V
• Resets Port PC0.
• Carries out all the Warm reset actions (see below).
• The PC87591L-N05 does not sample the value of any strap pin; instead, it maintains the configuration determined by
• It does not reset the TAP controller.
• On Debugger I/F, reset PC0 is not reset (it is reset on Watchdog reset).
• It resets the HFCG to its default frequency.
• Some MSWC registers do not reset on Watchdog or Debugger I/F reset.
PP
CC
bugger Interface reset and Software reset
is completed (after the HOSTWAIT bit in MCFG register is set to 1 by the Booter firmware) and the bus request can
be performed.
is completed.
the strap pins at V
is an internal power signal derived from V
Power-Up reset is generated by an internal circuit. The PC87591L-N05 performs a V
CC
Power-Up reset, the PC87591L-N05 responds as follows:
V
V
Watchdog Reset and Debugger Interface Reset
PP
PP
CC
retained functions: V
Power-Up Reset
Power-Up Reset
PP
is above V
CC
PP
Power-Up reset.
power. V
BATDTC
PP
PP
Power-Up reset
). When active, this signal resets all registers whose values are retained by V
IRST
Power-Up reset signal is active from the rising of V
CC
CC
Power-Up reset period.
CC
(Continued)
after the internal clocks have stabilized (see Section 7.6.2 on page 345).
Power-Up reset actions, with the following exceptions:
power-up, external devices should wait at least t
CC
and V
BAT
. V
62
PP
Power-Up reset is generated by an internal circuit that de-
CC
Power-Up reset, Warm reset, Watchdog reset, De-
CC
.
CC
PP
PP
Power-Up reset when V
until the V
.
32KW
before accessing the
PP
power is detected
CC
PP
Revision 1.2
.
pow-