pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 129

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
PS/2 Interrupt Enable Register (PSIEN)
The PSIEN register is an 8-bit read/write register. It enables/disables the various interrupts generated by the PS/2 module.
Bits in PSIEN register may be cleared to 0 only when interrupts are disabled (i.e., in the core, I or E bits in PSR register are
0) or when the corresponding interrupts in the ICU are masked. Bits in PSIEN register may be set to 1 at any time. On reset,
non-reserved bits of PSIEN are cleared.
Location: 00 FE8A
Type:
Bit
Name
Reset
7-3
Bit
Bit
0
1
2
0
1
2
3
4
5
6
7
RDAT1 (Read Data Signal Channel 1). The current value of the channel 1 data signal (PSDAT1).
RDAT2 (Read Data Signal Channel 2). The current value of the channel 2 data signal (PSDAT2).
RDAT3 (Read Data Signal Channel 3). The current value of the channel 3 data signal (PSDAT3).
RCLK1 (Read Clock Signal Channel 1). When read, returns the current value of the channel 1 clock signal
(PSCLK1).
RCLK2 (Read Clock Signal Channel 2). When read, returns the current value of the channel 2 clock signal
(PSCLK2).
RCLK3 (Read Clock Signal Channel 3). When read, returns the current value of the channel 3 clock signal
(PSCLK3).
RDAT4 (Read Data Signal Channel 4). The current value of the channel 4 data signal (PSDAT4).
RCLK4 (Read Clock Signal Channel 4). When read, returns the current value of the channel 4 clock signal
(PSCLK4).
SOTIE (Start of Transaction Interrupt Enable). Used for enabling the interrupt generation on a transaction
start detection.
0: SOT bit in PSTAT register does not affect the interrupt signal (default).
1: The interrupt signal (PSINT1) to the ICU is active (1) whenever SOT bit in PSTAT register is set.
Note: Once set, SOT is not cleared until the shift mechanism is reset. Therefore SOTIE should be cleared on
EOTIE (End of Transaction Interrupt Enable). Used for enabling the interrupt generation on an End of
Transaction detection.
0: EOT bit in PSTAT register does not affect the interrupt signal (default).
1: The interrupt signal (PSINT1) to the ICU is active (1) whenever EOT bit in PSTAT register is set.
Note: Once set, EOT is not cleared until the shift mechanism is reset. Therefore EOTIE should be cleared on
Disabled Shift Mechanism Interrupt Enable (DSMIE). Used for enabling the interrupt generation when the
shift mechanism is disabled.
0: The four interrupt signals are low. Note that PSINT1 may be activated (1) by other interrupt sources of the module
1: The clock input signals are connected to the Interrupt Control Unit (ICU), to allow implementing an interrupt driv-
Note: When the shift mechanism is disabled, no debounce is applied to the PSCLK inputs before producing the
Reserved.
R/W
(default).
en PS/2 protocol. The four interrupts generated are PSINT1, PSINT2, PSINT3 and PSINT4, for channels 1, 2,
3 and 4, respectively. Note that PSINT4 is connected to the MIWU and not directly to the ICU.
the first occurrence of an SOT interrupt. SOTIE should be set (1) when the PS/2 module is programed to
handle the impending transfer.
the first occurrence of an EOT interrupt. EOTIE should be set (1) when the PS/2 module is programed to
handle the impending transfer.
interrupt signals, except for local synchronization.
16
7
0
6
0
Reserved
5
0
(Continued)
Description
Description
129
4
0
3
0
DSMIE
2
0
EOTIE
1
0
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SOTIE
0
0