pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 284

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
5.5.4
In addition to its Power Management functions, the MSWC controls the handling of the following system control elements:
Host Configuration Address Selection
The standard strap configuration enables the selection of one of two SuperI/O configuration register addresses. When the
PC87591L-N05 is enabled in Programmable Configuration Address mode (see Table 37 on page 297), the core may set the
address of the SuperI/O configuration index/data registers.
HCFGBAL and HCFGBAH are byte-wide read/write registers. HCFGBAL holds the least significant byte of a host mother-
board PnP initial configuration address; HCFGBAH holds the most significant byte. The contents of HCFGBAH and HCFG-
BAL change only during V
To update the base address of the SuperI/O configuration index/data registers, do the following:
The base address is preserved by V
configuration base address, the LPC interface does not respond to configuration requests.
Host Keyboard Fast Reset
The Host Keyboard Reset output (KBRST) is an output of the PC87591L-N05 that serves as one of the sources for Host
Soft reset commands (i.e., INIT input in the x86 processors). Figure 99 shows the KBRST generation scheme. The host is
reset when the KBRST output is low. A reset command is issued by the PC87591L-N05 by software or hardware, as follows:
• Host Configuration Address Selection
• Host Keyboard Reset Fast Reset Output (KBRST)
• GA20 Pin Functionality
• Host Power on indication
• Software: The core firmware can issue a reset command to the host by writing 1 to HRSTOB in MSWCTL1 register.
• Hardware: The host is reset during V
1. Clear VHCFGA bit in MSWCTL1 register by writing 1 to it.
2. Write the lower byte of the address to HCFGBAL (LSB must be written 0).
3. Write the higher byte of the address to HCFGBAH.
4. Set HCFGLK bit to prevent an accidental change of the address written to HCFGBAL and HCFGBAH.
The reset to the host ends by writing 0 to this bit.
action is started. This is used to prevent accesses to the PC87591L-N05 from being ignored due to the duration of
the Power-Up reset.
HRAPU bit (MSWCTL3) =1
LPC Transaction Detected
HRSTOB bit (MSWCTL1)
V
CC
Other MSWC Controlled Elements
Power-Up Reset
From Host
I/F Module
Wake-Up
Module SMI
CC
Power-Up reset.
LPFTO bit (MSWCLT3) =1
PM2SMI
PM1SMI
Figure 99. KBRST Generation Scheme
CC
, and VHCFGA is set as long as a valid address is maintained. If there is no valid
Figure 98. SMI Source Gathering Scheme
CC
Power-Up reset if HRAPU bit in MSWCTL3 register is set and an LPC trans-
LPCPD = 0
(Continued)
284
Extend Logic
Host Reset
SMI
IOPB6
Logic
KBRST
Revision 1.2