pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 135

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Mode 4, Input Capture and Timer
It is also possible to operate in a mode that offers a combination of a single timer, with automatic reload, and a single capture
timer. In this mode, TnCNT1 operates as a timer that is reloaded from TnCRA on underflow while TnCNT2 forms the time
base of the capture timer. The value on TnCNT2 is transferred to TnCRB when a valid event on TBn is detected. It is possible
to toggle TA on every underflow of TnCNT1 and thus generate a 50% duty cycle signal on TAn.
This mode is a combination of modes 3 and 2. It allows timer/counter 2 to operate as a single-input capture timer concur-
rently with timer/counter 1. (Timer/counter 2 can be used as a system timer, as described in mode 3.) Figure 49 shows a
block diagram of the timer in mode 4.
TnCNT1 starts counting down once a clock has been enabled. On underflow, TnCNT1 is reloaded from TnCRA register, and
counting proceeds downwards from that value. If enabled, the TAn pin toggles on every underflow of TnCNT1. Software can
select the initial value of the TAn output signal as either high or low (see Section 4.7.5 on page 137 for additional details).
In addition, the TnAPND interrupt pending flag is set, and a timer interrupt 1 is generated if TnAIEN bit is set to 1 (see
Section 4.7.4 on page 136 for detailed information). Since TAn toggles on every underflow, a 50% duty cycle signal can be
generated on TAn without requiring any interaction of software (and therefore the core).
TnCNT2 starts counting down once a clock has been enabled. When a transition is received on TBn, the value contained in
TnCNT2 is transferred to TnCRB, and the interrupt pending flag, TnBPND, is set. A timer interrupt 2 is generated if it is en-
abled. A preset of the counter to FFFF
of TnCNT2 is transferred to TnCRB, followed by a preset of the counter to FFFF
FFFF
derflow of TnCNT2 sets the TnDPND interrupt pending flag and can also generate a timer interrupt 2 if the interrupt was
enabled (see Section 4.7.4 on page 136 for detailed information.). The input signal on TBn must have a pulse width equal
to or greater than one system clock cycle (see Section 7.6.10 on page 358 for additional details). TBn can be configured to
sense either rising or negative edge transitions.
Note that TnCNT2 can not operate in the Pulse Accumulate or External Event Counter modes since TBn input is used as a
capture input. Selecting either Pulse Accumulate mode or External Event Counter mode for TnCNT2 causes TnCNT2 to stop.
Note, however, that all available clock source modes may be selected for TnCNT1. Thus it is possible to use TnCNT1 to
determine the number of capture events on TBn or the elapsed time between capture events on TBn.
16
Timer 1
Timer 2
Selector
Clock
Clock
Clock
until the next transition is received on TBn, which causes the procedure of capture and preset to be repeated. Un-
Figure 48. Mode 3, Dual Independent Timer
16
Timer/Counter 1
on detection of a transition on TBn can be enabled. In this case, the current value
Timer/Counter 2
TnCNT1
Reload A
Reload B
TnCRA
TnCNT2
TnCRB
(Continued)
Underflow
Underflow
135
16
TAPND
TDPND
. TnCNT2 starts counting downwards from
TDIEN
TAIEN
TAEN
Interrupt 2
Interrupt 1
Timer
Timer
TA
T
Bn
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