pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 56

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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2.0 Signal/Pin Description and Configuration
2.4.3
Some of GPIO pins may be paired to generate an input to output echoing with software masking. The input GPIO are input
ports (Px or Py) with a wake-up function. The output ports are a Px type enhanced with the echo mechanism, as described
in Section 4.5.2 on page 111. The input echoing is enabled only when the respective Echo Enable bit in IOEE1-2 registers
is set. The input port should be configured to enable the interrupt function.
Input to Output Echo Enable Register 1 and 2 (IOEE1 and IOEE2)
The IOEE1 and IOEE2 registers are read/write, byte-wide registers. They enable the echoing of some of the General-Pur-
pose Input ports, equipped with wake-up, to a specified output. The IOEE bits have an impact only when the output GPIO
is configured to its GPIO function. IOEE1 and IOEE2 are cleared (00
The format of IOEE1 is:
IOEE1 Location: 00 FF02
Type:
Bit
Name
Reset
7-3
Bit
0
1
2
GPIO with Echo Configuration
ENUSART2 (Enable USART2). This bit selects either the USART2 or PS/2 Channels 3 and 4 to device pins.
When set, this bit enables the use of USART2.
0: PS/2 Channels 3 and 4 or IOPF4-6 signals are selected, according to PFALT4-6 bits (default)
1: USART2 signals are selected
A19 (Enable A19). This bit selects between either A19 or IOPL3 to the device pin. When set to 1, A19 bit
enables the use of A19.
0: IOPL3 signal is selected
1: A19 signal is selected (default)
A20 (Enable A20). This bit selects either A20 or IOPE5/EXWINT40 to the device pin. When set to 1, A20 bit
enables the use of A20.
0: IOPE5/EXWINT40 signal is selected, according to PEALT5 bit (default)
1: A20 signal is selected
Reserved.
R/W
7
0
Output Port
Table 7. GPIO Echo Functions Routing and Echo Enable Bit Assignments
IOPC0
IOPD3
IOPB0
IOPB1
IOPB2
IOPA0
IOPA1
IOPA2
IOPA3
IOPA4
16
Reserved
6
0
EEPC0 bit in IOEE2 register
EEPB0 bit in IOEE2 register
EEPB1 bit in IOEE2 register
EEPB2 bit in IOEE2 register
EEPD3 bit in IOEE2 register
EEPA0 bit in IOEE1 register
EEPA1 bit in IOEE1 register
EEPA2 bit in IOEE1 register
EEPA3 bit in IOEE1 register
EEPA4 bit in IOEE1 register
Echo Enable Bit
5
0
EEPA4
Description
56
4
0
(Continued)
16
IOPE7/CLKRUN/EXWINT46
) on reset.
IOPE6/LPCPD/EXWINT45
EEPA3
3
0
IOPC4/EXWINT22
IOPD0/EXWINT20
IOPD1/EXWINT21
IOPC6/EXWINT23
IOPD2/EXWINT24
IOPF6/PSCLK4
IOPF7/PSDAT4
IOPE4/SWIN
Input Port
EEPA2
2
0
EEPA1
1
0
EEPA0
0
0
Revision 1.2