pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 123

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Shift Status
The PSTAT register indicates the current status of the shift mechanism. The data transfer process may be in one of the
following three states:
Input Signal Debounce
The PC87591L-N05 performs a debounce operation on the clock input signal before determining its logical value. IDB field
in PSCON register determines for how many clock cycles the input signal must be stable to define a change in its value.
Interrupt Generation
The PSINT1 is an interrupt signal generated by the shift mechanism to allow an interrupt driven interface with the firmware.
The ICU should be programed to detect high-level interrupts on the PSINT1 interrupt. See Section 4.3 on page 96 for details
on the ICU. SOTIE and EOTIE bits in PSIEN register mask the interrupt signaling for SOT and EOT bits, respectively, in
PSTAT register.
Receive Mode
Receive Inactive
When the shift mechanism is enabled and bit XMT=0 in PSCON register, the shift mechanism enters Receive mode in the
Receive Inactive state. Receive Idle state is entered when one (or more) of the channels is enabled, by setting the channel
enable bit (CLK4-1 for channels 4-1, respectively). In this state, the shift-mechanism sets the clock and data lines of the
enabled channels high (1) and waits for a start bit.
Receive Idle
In the Receive Idle state, the PS/2 interface waits for input from any one of the enabled channels. The first of the enabled
channels to send a start bit is selected for handling by the shift mechanism. The other two channels are disabled by forcing
‘0’ on their clock lines.
Start Bit Detection
The start bit is identified by a falling edge on the clock signal while the data signal is low (0).
If the start bit is identified simultaneously in more than one channel, one channel is selected for receive, while the other chan-
nel’s transfer is aborted. The channel with the lower number is selected (i.e., channel 1 has priority over channels 2, 3 and
4, channel 2 has priority over channel 3 and 4 and channel 3 has priority over channel 4). The data transfer in the other
channels is aborted before 10 data bits have been sent (by forcing the clock signal to 0), and the transmitting PS/2 device
resends its data when its interface is enabled again by the firmware. This mechanism ensures that no incoming data is lost.
When the hardware sets (1) SOT bit and designates the selected channel in ACH field, this indicates receipt of the start bit
in PSTAT register. In addition, if SOTIE is set in PSIEN register, an interrupt signal to the ICU is set high. The firmware may
use this interrupt to start a time-out timer for the data transfer.
Receive Active
After identifying the start bit, the shift mechanism enters the “Receive-Active” state. In this state the clock signal of the se-
lected device (PSCLK1, PSCLK2, PSCLK3 or PSCLK4) sets the data bit rate. On each falling edge of the clock, new data
is sampled on the data signal of the active channel (i.e., PSDAT1 PSDAT2, PSDAT3 or PSDAT4).
Following the start bit, eight bits of data are received (clocks 2 through 9); a parity bit follows (10th clock) and then a stop bit
(11th clock). The stop bit is indicated by a falling edge of the clock with the data signal high (1). If the 11th clock is identified
with data low, the receive frame error bit (RFERR in PSTAT register) is set but the clock is treated as the stop bit.
After the parity is received, the shift mechanism checks the incoming data for parity errors. If there are eight data bits with a
value of 1 and the parity bit is even, PERR bit in PSCON register is set, indicating a parity error.
• Shifter Empty:
• Start Bit Detected:
• End of Transaction:
The shift mechanism is in Receive Inactive, Receive Idle, Transmit Inactive or Transmit Idle state. The PSTAT is
cleared because none of the enabled devices has sent a start bit.
The shift mechanism is in Receive Active or Transmit Active state. This indicates that a start bit was identified for at
least one of the channels and the shift process has begun. SOT bit in PSTAT register indicates the detection of the
start bit and ACH field in PSTAT register indicates the active channel (the channel on which the start bit was detect-
ed).
The shift mechanism is in End-of-Reception or End-of-Transmission state. This indicates that the last bit of the trans-
fer sequence was detected (and the data can therefore be read from PSDAT register) or that the data transmission
was completed (for receive and transmit, respectively). EOT bit in PSTAT register indicates transfer completion. If a
parity error was detected in the received data, PERR bit in PSTAT register is set. If a stop bit was detected low in-
stead of high, RFERR bit in PSTAT register is set.
(Continued)
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