pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 249

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Modules
Host Interface Keyboard/Mouse Status Register (HIKMST)
The HIKMST register provides the status of the Host Interface keyboard channel buffers (DBBIN and DBBOUT) and a way
for the PC87591L-N05 to send status bits to the host. This register can also be read by a host processor read operation from
address 64
Location: 00 FEA4
Type:
Host Interface Keyboard Data Out Buffer Register (HIKDO)
The HIKDO register allows the core firmware to write to DBBOUT register while setting OBF bit in the Status register. If IRQ1
interrupt is enabled, it is sent. If the core interrupt on output buffer empty is enabled (OBECIE in HICTRL register is 1), writing
to HIKDO de-asserts it (low).
Location: 00 FEA6
Type:
Bit
Name
Reset
Bit
Name
7-4
7-0
Bit
Bit
Bit
6
7
0
1
2
3
IRQNPOL (Negative Polarity). When IRQNPOL is cleared, the IRQ (IRQ1, IRQ11, IRQ12) signal polarity is
compatible with the standard ISA bus interface (as specified in the IRQM field). When hardware IRQ generation
is enabled (HICTRL register bits OBFKIE for IRQ1 and IRQ12; PMHIE for IRQ11), the interrupt output is
inverted if IRQNPOL is set.
Reserved.
OBF (Output Buffer Full). The bit is set when the keyboard/mouse channel’s DBBOUT is written by the core
(i.e., writing to HIKDO or HIMDO register). The bit is cleared by a host processor read from the keyboard/mouse
channel output buffer (60
IBF (Input Buffer Full). The bit is set when the keyboard/mouse channel’s DBBIN is written by the host
processor, i.e., writing to either address 60
of the input buffer (HIKMDI). This read-only bit is ignored when writing to this register.
F0 (Flag 0). A general-purpose flag that can be set or cleared by the core firmware.
A2 (A2 Address). Holds the value of the A2 signal in the last write operation of the host to the keyboard/mouse
channel’s input buffer (i.e., indicates A2 value during write to address 60
when writing to this register.
ST3-ST0 (Status Bits). Four general-purpose flags that can be set or cleared by the core firmware.
Keyboard DBBOUT Data.
R/W
WO
16
. On reset, the register is cleared.
16
16
7
7
6
6
16
ST3-ST0
). This read-only bit is ignored when writing to this register.
0
5
5
16
(Continued)
Keyboard DBBOUT Data
(data) or address 64
Description
Description
Description
249
4
4
A2
3
0
3
16
(control). The bit is cleared by a core read
16
or 64
F0
2
0
2
16
). This read-only bit is ignored
IBF
1
0
1
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OBF
0
0
0