pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 295

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Module
MSWC Host Event Interrupt Enable Register (MSHEIE0)
This register is cleared to 00
bit in the MSHES0 register. The interrupt may be cleared by clearing the status bit or masking the interrupt.
Location: Offset 00 FCD0
Type:
Bit
Name
Reset
5-4
5-4
Bit
Bit
3
6
7
0
1
2
3
6
7
RING Event Status. RING event detection, according to the RING detection mode enabled.
0: Event not detected (default)
1: Event detected
Reserved.
Software Event Status. This bit indicates a host software event. It may operate in two modes depending on
HSECM bit in MSWCTL1 register.
When HSECM is cleared, this bit is set when bit 6 of WK_STS0 changes from 0 to 1.
When HSECM is set, this bit is set on a write of 1 to WK_STS0 bit 1. This bit is cleared by writing 1 to it.
0: Event not active (default)
1: Event active
Module IRQ Event Status. This sticky bit shows the status of the module IRQ event detection.
0: Event not active (default)
1: Event active
RI1 Event Enable.
0: Disabled (default)
1: Enabled
RI2 Event Enable.
0: Disabled (default)
1: Enabled
Reserved.
RING Event Enable.
0: Disabled (default)
1: Enabled
Reserved.
Software Event Enable.
0: Disabled (default)
1: Enabled
Module IRQ Event Enable.
0: Disabled (default)
1: Enabled
R/W
Module IRQ
Enable
Event
7
0
16
16
Software
Enable
Event
on Warm reset. It enables a core interrupt through the MIWU (level high) for the respective
6
0
5
0
Reserved
(Continued)
Description
Description
295
4
0
Enable
Event
RING
3
0
Reserved
2
0
Enable
Event
RI2
1
0
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Enable
Event
RI1
0
0