pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 165

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Watchdog Count Register (WDCNT)
The WDCNT register is a byte-wide, write-only register. It holds the value loaded into the watchdog timer when it is touched
and counts down from it. The watchdog is started by the first write to the register. Each successive write restarts the watch-
dog timer. A write to WDCNT functions as a touch operation when WDSDME bit TWCFG register is cleared, even if WDCNT
is locked; in this case, the watchdog timer is restarted using the value loaded in PRESET field before WDCNT was locked
(i.e., the new PRESET value is ignored). On reset this register is initialized to 0F
Location: 00 FEE8
Type:
Watchdog Service Data Match Register (WDSDM)
The WDSDM register is a byte-wide, write-only register. When WDSDME in TWCFG register is set, the watchdog counting
restarts from the value in WDCNT, when WDSDM is written with 5C
a watchdog signal. If RSDATA is written more than once per three watchdog clock cycles, a watchdog signal is also trig-
gered. When the WDSDME bit is cleared, a write to this register is ignored.
Location: 00 FEEA
Type:
4.10.4 Usage Hints
The TWD protects watchdog operation from software tampering. To achieve the highest level of protection, proceed as fol-
lows:
1. Program the TWDT0 pre-scale and TMWT0 timers to the desired values.
2. Configure the watchdog clock to use T0IN or T0OUT using WDCT0I bit in TWCFG register.
3. Program the WDCTL to the maximum period between watchdog touch operations. Note that from this point, the watch-
4. Configure the watchdog to use data match, and lock all the TWD configuration and setting registers by setting bits 0
5. Touch the watchdog by writing 5C
Bit
Name
Reset
Bit
Name
7-0
7-0
Bit
Bit
dog starts operating and must be touched periodically to prevent a watchdog error signal.
through 4 and bit 6 of the TWCFG.
cycle and no less than the period programed to WDCTL).
PRESET. Defines the counter preset value.
RSDATA.
WO
WO
16
16
7
0
7
6
0
6
16
to WDSDM at the appropriate rate (i.e., no more than once every watchdog clock
5
0
5
(Continued)
Description
Description
165
4
0
4
PRESET
RSDATA
16
. If any other data is written to this register, it triggers
3
1
3
16
.
2
1
2
1
1
1
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0
1
0