pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 168

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
4.0 Embedded Controller Modules
Use the equations in the following table to calculate the input voltage based on the reading from the Voltage Channel Data
result (VCHDAT field in VCHNxDAT register).
The input voltage is converted to Voltage Channel Data result (VCHDAT field in VCHNxDAT register) according to the fol-
lowing table:
Changing the input selection for a new measurement requires switching between inputs at different voltage levels. The input
interface circuits of the ADC, together with the externally added noise-rejection filters (if applicable), requires a settling time
to reach the new voltage value with 8-bit accuracy (less than 1/2 LSB error). Therefore, the ADC waits for a programmable
delay time between the selection of the input to be measured and the beginning of the A/D conversion. This Voltage Channel
Delay is expressed in ADC clock cycles in ADC Delay Control register (ADLYCTL). The number of ADC clock cycles should
be converted to time using the following formula:
To calculate the required delay value according to externally added components, see Section 4.11.6 on page 176.
4.11.4 ADC Operation
Reset
Section 3.2 on page 61 describes the types of PC87591L-N05 resets. The ADC is affected by the core domain reset events,
as described below:
All control, configuration and status registers are reset to their default values, as indicated in Section 4.11.5 on page 171.
The Voltage (1, 2 and 3) Channel Data Buffer registers are not reset, since their value is undefined until the first measure-
ment occurs (on each of them).
The ADC is disabled, with all interrupt sources masked and all event status bits reset. The clock division factor, as well as
the voltage channel delay, are all set to their maximum value (for the slowest ADC operation speed). Each of the three chan-
nels is individually disabled, along with its interrupt source. The Selected Input for all three voltage channels is set to 1F
(disabled).
ADC Clock
The ADC clock is generated by dividing the system clock by a factor in the range of 4 to 63, as defined in SCLKDIV field in
ACLKCTL register (see Section 4.11.5 on page 171). The system clock’s source is the on-chip clock multiplier (see
Section 4.18 on page 212). The ADC clock needs to be at a frequency of 0.5 MHz. SCLKDIV must be programed prior to
enabling the ADC (i.e., while ADCEN of the ADCCNF register is 0).
Initializing the ADC
The ADC must be initialized before it is enabled. The following steps need to be taken to initialize it before enabling the ADC
(i.e., ADCEN bit in ADCCNF register is cleared):
• System Clock Division Factor - SCLKDIV field in ACLKCTL register.
• Voltage Channel Delay - VOLDLY field in ADLYCTL register.
AD0 to AD9
AD0 to AD9
AD10 to AD13
Input Channel
1. See Section 7.4.1 on page 340 for the dynamic range relevant for each input.
2. No Scale (High or Low) is defined for these inputs.
3. These inputs are scaled down by 4 at the input and compensated back at the result read phase.
t
VD
= Number_of_ADC_clocks
Low
High
-
2,3
0V (ground)
(255/256)
Scale
Input Voltage
Vi = VCHDAT(9-2) * (1 / 256) * V
Vi = VCHDAT(9-2) * (1 / 256) * V
Vi = VCHDAT(9-2) * (1 / 256) * V
*
V
FS
(Continued)
VCHDAT(9-2) = 00
VCHDAT(9-2) = FF
*
(System_clock_cycle)
168
Result
Calculation
16
16
FSL
FSH
FSV
1
*
SCLKDIV(5-0)
Revision 1.2
16