pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 186

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
There are two exceptions to the “acknowledge after every byte” rule:
Addressing Transfer Formats
Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave
being addressed. The slave device should send an Acknowledge signal on the SDAn line once it recognizes its address.
The address consists of the first seven bits after a Start Condition. The eighth bit contains the direction of the data transfer
(R/W). A low-to-high transition during a SCLn high period indicates the Stop Condition and ends the transaction of SDAn
(Figure 70).
When the address is sent, each device in the system compares this address with its own. If there is a match, the device
considers itself addressed and sends an Acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the
device acts as a transmitter or a receiver.
The I
the general call address (00
software only”). Slaves that require data acknowledge the call and become slave receivers; other slaves ignore the call.
Arbitration on the Bus
Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is
initially determined according to address bits and clock cycle. If more than one master tries to address the same slave, data
comparisons determine the outcome of this arbitration. In Master mode, the device immediately aborts a transaction if the
value sampled on the SDAn line differs from the value driven by the device. (An exception to this rule is SDAn while receiving
data; in this case, the lines may be driven low by the slave without causing an abort.)
The SCLn signal is monitored for clock synchronization to allow the slave to stall the bus. The actual clock period is the long-
est one set by the master or the slave stall period. The clock high period is determined by the master with the shortest clock
high period.
When an abort occurs during address transmission, a master that identifies the conflict should give up the bus and switch
to Slave mode. It should then continue to sample SDAn to see if it is being addressed by the winning master on the bus.
4.13.3 Master Mode
Requesting Bus Mastership
An ACCESS.bus transaction starts with a master device requesting bus mastership. It asserts a Start Condition, followed by
the address of the device it wants to access. If this transaction is successfully completed, the software may assume that the
device has become the bus master.
For the device to become the bus master, the software should perform the following steps:
1. Configure INTEN in ACBnCTL1 register to the desired operation mode (Polling or Interrupt) and set START in the same
2. If a bus conflict is detected (i.e., some other device pulls down the SCLn signal before the PC87591L-N05 does), BER
3. If there is no bus conflict, MASTER and SDAST in ACBnST register are set.
4. If INTEN in ACBnCTL1 register is set and either BER or SDAST in ACBnST register is set, an interrupt is sent to the core.
• When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging (negative
• When the receiver is full or otherwise occupied, or if a problem occurs, it sends a negative acknowledge to indicate
acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the Acknowledge clock
pulse (generated by the master), but the SDAn line is not pulled down.
that it cannot accept additional data bytes.
register. This causes the ACB to issue a Start Condition on the ACCESS.bus as soon as the ACCESS.bus is free (some
conditions, such as when BB in ACBnCST register is set to 0, can delay start). It then stalls the bus by holding SCLn low.
in ACBnST register is set.
2
C bus protocol allows a general call address to be sent to all slaves connected to the bus. The first byte sent specifies
SDAn
SCLn
Start
Condition
16
S
); the second byte specifies the general call meaning (for example, “Write slave address by
Figure 70. A Complete ACCESS.bus Data Transaction
Address R/W ACK
1 - 7
8
(Continued)
9
1 - 7
Data
186
8
ACK
9
1 - 7
Data
8
ACK
9
Stop
Condition
P
Revision 1.2