pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 7

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
Table of Contents
3.0
4.0
2.3
2.4
Power, Reset and Clocks
3.1
3.2
3.3
3.4
Embedded Controller Modules
4.1
2.2.12
2.2.13
2.2.14
2.2.15
STRAP PINS ............................................................................................................................. 48
ALTERNATE FUNCTIONS ........................................................................................................ 49
2.4.1
2.4.2
2.4.3
POWER ..................................................................................................................................... 58
3.1.1
3.1.2
3.1.3
RESET SOURCES AND TYPES ............................................................................................... 61
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
CLOCK DOMAINS ..................................................................................................................... 64
TESTABILITY SUPPORT .......................................................................................................... 64
3.4.1
3.4.2
BUS INTERFACE UNIT (BIU) ................................................................................................... 67
4.1.1
4.1.2
Mobile System Wake-Up Control (MSWC) ................................................................. 46
Timers and PWM ....................................................................................................... 46
Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ...................... 46
Internal Pull-Up and Pull-Down Resistors ................................................................... 47
GPIO with Alternate Functions .................................................................................... 49
System Configuration Registers .................................................................................. 52
GPIO with Echo Configuration ..................................................................................... 56
Power Planes .............................................................................................................. 58
Power States ............................................................................................................... 58
Power Connection and Layout Guidelines .................................................................. 59
V
V
Watchdog Reset and Debugger Interface Reset ......................................................... 62
Warm Reset ................................................................................................................. 63
Host Domain Reset ..................................................................................................... 63
ICT ............................................................................................................................... 64
XOR-Tree Testing ....................................................................................................... 64
Features ...................................................................................................................... 67
Functional Description ................................................................................................. 67
(Continued)
PP
CC
Setting the Environment ......................................................................................... 48
Other Strap Pin Settings ......................................................................................... 48
System Load on Strap Pins .................................................................................... 48
Strap Pin Status Register (STRPST) ..................................................................... 48
Register Map .......................................................................................................... 52
Module Configuration Register (MCFG) ................................................................. 52
External Interrupts Configuration Register (EICFG) ............................................... 53
Protection Word Low Register (PTWRL) ................................................................ 54
Protection Word High Register (PTWRH) .............................................................. 55
Pin Multiplexing Register (PNMR) .......................................................................... 55
Input to Output Echo Enable Register 1 and 2 (IOEE1 and IOEE2) ...................... 56
Using RESET2 Input .............................................................................................. 63
Host Domain Reset Actions ................................................................................... 63
Core Domain Clock ............................................................................................... 64
LPC Clock .............................................................................................................. 64
RTC (32 KHz) Clock ............................................................................................... 64
Interface ................................................................................................................. 67
Power-Up Reset ................................................................................................... 62
Power-Up Reset ................................................................................................... 62
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