pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 32

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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1.0 Introduction
The core boot section is stored in the base memory. This memory is:
The constant data and the remaining core code is stored in external expansion memory, which is one of the following:
The on-chip RAM and various peripherals are also mapped into the core address space.
Table 1 shows how the PC87591L-N05 memory and I/O devices are mapped in the core address space. Appendix A on
page 367 shows the address map of the registers for the other modules.
Addresses not included in the following table or Appendix A are reserved. Attempts to access reserved addresses produce
unpredictable results
Register Abbreviations and Access
The following abbreviations are used to indicate the Register Type:
Either byte-wide or word-wide transactions to any address within the memory address space may be used to access memory
devices.
Only byte-wide transactions may be used to access byte-wide registers, and only word-wide transactions may be used to
access word-wide registers. Attempts to read a write-only register or write to a read-only register cause unpredictable re-
sults.
Zeros must be written to reserved bits unless stated otherwise. Reading reserved bits returns an undefined value. When
modifying a register with reserved bits, the data read from reserved a bit can be written back to it.
• On-chip ROM in IRE and OBD environments
• Off-chip memories (SRAM or flash memory) in DEV environment
• Flash memory in IRE and OBD environments
• SRAM or flash memory in DEV environment
• R/W= Read/Write
• R= The Read portion of a register, where a read from a specific address returns the value of a specific register; a
• W= The Write portion of a register as described above for ‘R’.
• RO= Read Only
• WO= Write Only
• R/W1C= Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
00 FB00
00 FC00
00 1000
00 E800
01 0000
00 0000
00 F900
00 F980
00 FA00
00 F880
write to the same address is to a different register.
1. Zone 2 is enabled by bit 5 of Module Configuration Register (MCFG) (see Page 52). The size of zone 2 is
2. The system RAM size is controlled by bit 7 of the PTWRH register (see Page 55).
3. See Appendix B on page 393 for details of the implemented registers.
4. See Appendix A on page 367 for details of the implemented registers.
5. See “Accessing I/O Expansion Space” on page 34.
selected by bits 0-1 of the PTWRH register (see Page 55).
Address
16
16
16
16
16
16
16
16
16
16
00 DFFF
1F FFFF
00 0FFF
00 F90A
00 FBFF
00 F7FF
00 F883
00 F98F
00 FA7F
00 FFFF
.
(Continued)
16
16
16
16
16
16
16
16
16
16
(Bytes)
1984K Expansion Memory (Zone 0 or Zone 2
Size
52K
256
4K
4K
1K
11
16
4
Base Memory
Expansion Memory (Zone 0 or Zone 2
System RAM
Information Block Access Registers
Shared BIOS and Protection Registers
BIU Registers
DMA Controller Registers
I/O Expansion
On-Chip Module Registers
Table 1. PC87591L-N05 Memory Map
2
4
5
Purpose
32
4
4
Description
3
1
1
4
)
)
IRE & OBD - Internal ROM
DEV - External Base Memory (Zone 1)
Environment
Revision 1.2