pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 271

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Modules
5.3.8
The following set of registers is accessible only by the core. These registers are maintained by V
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
Shared Memory Core Register Map
Shared Memory Core Control and Status Register (SMCCST)
This register provides control and status of read/write from/to a restricted address. The register is cleared (00
Location: 00 F900
Type:
Bit
Name
Reset
4-3
Bit
0
1
2
5
6
7
SMCCST
SMCTA
SMHSEM
SMCORP0-2
SMCOWP0-2 Shared Memory Core Override Write Protect 0-2
Shared Memory Core Registers
HRERR (Host Read Error). The bit is set (1) when the host attempts to read from a read-protected block or
out-of-range address. An out-of-range address is an address that the LPC configuration module defines as
mapped to the PC87591L-N05, but it is actually translated to a reserved address in the core address space.
Writing 1 to this bit clears it to 0. Writing 0 has no effect.
HWERR (Host Write Error). The bit is set (1) when the host attempts to write to a read-protected block or out-
of-range address. An out-of-range address is an address that the LPC configuration module defines as mapped
to the PC87591L-N05, but it is actually translated to a reserved address in the core address space. Writing 1
to this bit clears it to 0. Writing 0 has no effect.
HERRIEN (Host Error Interrupt Enable). When set (1) and either the HRERR or HWERR bit is set (1), a core
interrupt is generated; otherwise, the core interrupt is inactive.
HERES (Host Error Response). Controls response type on read/write from/to a protected block or out-of-range
address. An out-of-range address is an address that the LPC configuration module defines as mapped to the
PC87591L-N05, but it is actually translated to a reserved address in the core address space.
Bits
4 3
0 0:
0 1:
1 0:
1 1:
HLOCK (Host Lock).
0: The bridge does not generate write transactions on the core bus (default)
1: The bridge can generate write transactions on the core bus
HSEMW (Host Semaphore Write). The bit is set (1) when the host writes to HSEM register. Writing 1 to this
bit position clears it to 0. Writing 0 has no effect.
HSEMIE (Host Semaphore Interrupt Enable). When the bit is set (1), the interrupt to the core is set (level
high) if HSEMW is set.
Mnemonic
R/W
HSEMIE
7
16
0
Description
Drive Long Wait for read; ignore write (default)
Read back 00
Drive error SYNC for both read and write
Reserved
Shared Memory Core Control and Status
Shared Memory Core Top Address
Shared Memory Host Semaphores
Shared Memory Core Override Read Protect 0-2
HSEMW
6
0
16
; ignore write
HLOCK
Register Name
5
0
(Continued)
Description
271
4
0
HERES
3
0
RO in IRE and OBD environments;
HERRIEN
R/W in DEV environment
2
0
Varies per bit
R/W or RO
R/W or RO
Type
R/W
CC
HWERR
.
1
0
16
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) on reset.
HRERR
0
0