pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 272

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
Shared Memory Core Top Address Register (SMCTA)
This register provides information about the size of the on-chip main block. The register is loaded with its default value on
V
Location: 00 F902
Type:
Shared Memory Host Semaphore Register (SMHSEM)
This register provides eight semaphore bits between the core and the host. Four of the bits may be set by the host; four may
be set by the core. The register is cleared (00
Location: 00 F904
Type:
Shared Memory Core Override Read Protect Registers 0-2 (SMCORP0-2)
SMCORP0-2 are 16-bit registers that provide core override on the host read protection bits. For the host to be able to read
a memory location, both the Host Read Protection bit (controlled through the Shared Memory Host Access Protect Register
1 or 2) and the associated bit in SMCORP0-2 should be cleared. Each bit in this register is associated with a memory block,
as described in the bits description. Bits in these registers may be RO or RW depending on their position and the size of the
core and host boot blocks. SMCORP0-2 registers are loaded with reset values either on reset or when the value of SMCTA
register is changed; the reset values depend on the size of the core and host boot blocks, as defined in PTWRL register.
Location: 00 F910
Type:
Bit
Name
Reset
Bit
Name
Reset
Bit
Name
Reset
CC
4-0
7-5
3-0
7-4
Bit
Bit
Power-Up reset only.
MBSD (Main Block Size Definition). Defines the size of the main block in 64 Kbyte units. Thus the MBTA value
is MBSD * 1 0000
The reset value of this field is affected by the Force MBTA Zero bit in PTWRL register (see Page 54). When the
Force MBTA Zero bit is set, the reset value of this field is 0
shown in the bit table, above.
This field is loaded on V
loaded with a new value.
Reserved.
Type
R/W CSEM3-0. Four bits that may be updated by the core and read by both the host and the core.
RO
RO in IRE and OBD environments
R/W in DEV environment
Varies per bit
R/W or RO as described in the description below
15
CSEM3
HSEM3-0. Four bits that may be updated by the host and read by both the host and the core.
16
16
16
7
0
, 00 F912
14
7
0
16
See bit description below
13
. Note that MBTA is actually the first address beyond the main block.
CSEM2
Reserved
16
, 00 F914
6
CC
0
6
12
0
Power-Up reset with the on-chip ROM size. In DEV environment, the MBSD may be
11
16
CSEM1
16
5
0
) on reset.
5
0
10
(Continued)
9
CSEM0
Description
272
4
0
ORPLA15-0
4
Description
8
16
7
1
HSEM3
; when the bit is cleared, the reset value is as
2 (see note in field description)
3
0
3
6
HSEM2
5
See bit description below
MBSD
2
0
2
4
HSEM1
3
1
0
1
2
HSEM1
1
0
0
0
Revision 1.2
0