pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 280

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
5.5
The MSWC detects and handles wake-up events from various sources in the host-controlled modules. The MSWC gener-
ates interrupts to the host via SMI or PWUREQ, and/or alerts the core, which enables the core to control the wake-up se-
quence. Since the MSWC is powered by V
depend on the presence of a clock; these functions are not available when the core clock is turned off.
Figure 95 shows the block diagram of the MSWC.
5.5.1
The MSWC recognizes the following maskable system events:
The MSWC notifies the host and/or core when any of the above events occur by asserting one or more of the following output
pins:
5.5.2
The MSWC monitors various system signals for a wake-up event. When an event is detected, a status bit is set to record it.
Each event goes to the Wake-Up Mode Control Logic, which determines its effect (see Figure 97 for an illustration of this
mechanism). A set of dedicated registers is used to determine the wake-up criteria, including the RING detection mode.
The following wake-up input events are detected by the MSWC:
• Modem ring (RI1 and RI2 pins)
• Telephone ring (RING input pin)
• Wake-up on module IRQs for RTC, KBD and Mouse
• Software events
• Power-Up Request (PWUREQ)
• System Management Interrupt (SMI)
• Interrupt to the host (IRQ)
• MSWC interrupt to the core
• Software events
• IRQ from SuperI/O modules
• Modem Ring (RI1 and RI2)
• Telephone Ring (RING input)
• ACPI state change
• Legacy off event
• RTC Alarm
— Software triggered wake-up event
— ACPI power state change indications
— Software off command
Modules’ IRQs
RI1 RI2
RING Input
Off Event
RTC Alarm
MOBILE SYSTEM WAKE-UP CONTROL (MSWC)
Features
Wake-Up Event Detection and Status Bits
Host Domain Internal Bus
Core Peripheral Bus
Detection
Wake-Up
Event
Configuration
Control &
Registers
Figure 95. MSWC Block Diagram
CC
, it can operate in low power consumption states. Some MSWC operations
Configuration
Wake-Up
(Continued)
MSWC Interrupt
280
Status Registers
SMI
PWUREQ
SMI
IRQ
PM I/F
Channels
Revision 1.2