pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 93

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
11-10 INCA (Increment/Decrement ADCAn).
14-13 INCB (Increment/Decrement ADCBn).
Bit
12
15
1
2
3
4
5
6
7
8
9
ETC (Enable Interrupt on Terminal Count). This bit enables a level interrupt, when TC bit is set.
0: Interrupt masked (default)
1: Interrupt enabled
EOVR (Enable Interrupt on OVR). This bit enables a level interrupt, when OVR bit is set.
0: Interrupt masked (default)
1: Interrupt enabled
TCS (Transfer Cycle Size). This bit specifies the number of bytes transferred in each DMA transfer cycle. In
Direct (Fly-By) mode, undefined results occur if TCS is not equal to the addressed memory bus width.
0: Byte wide transfer (default)
1: Word-wide (16-bit) transfer
IND (Direct/Indirect Transfer). This bit sets the Transfer Type.
0: Direct (Fly-By- default)
1: Indirect (Memory-to-Memory)
DIR (Transfer Direction). This bit specifies the direction of the transfer relative to Device A.
0: Device A (pointed to by ADCAn) is the source. In Fly-By mode, a read transaction is initialized.
1: Device A (pointed to by ADCAn) is the destination. In Fly-By mode, a write transaction is initialized.
OT (Operation Type).
0: Single-Buffer mode or Double-Buffer mode enabled (default)
1: Auto-Initialize mode enabled
BPC (Bus Policy Control). This bit sets the operation type, intermittent (cycle stealing) or continuous (burst).
0: Intermittent operation. DMAC channel n relinquishes the bus after each transaction even if the request is still
1: Continous operation. DMAC channel n uses the bus continuously as long as the request is asserted. This mode
SWRQ (Software DMA Request).
0: Software DMA request is inactive (default)
1: Software DMA request is active
ADA (Device A Address Control). This bit enables Update of Device A Address.
0: ADCAn address unchanged (default)
1: ADCAn address incremented or decremented, according to INCA field
Bits
11 10 Description
ADB (Device B Address Control). This bit enables Update of Device B Address.
0: ADCBn address unchanged
1: ADCBn address incremented or decremented, according to INCB field
Bits
14 13 Description
Reserved.
0 0: Increment ADCAn register by 1 (default)
0 1: Increment ADCAn register by 2
1 0: Decrement ADCAn register by 1
1 1: Decrement ADCAn register by 2
0 0: Increment ADCBn register by 1 (default)
0 1: Increment ADCBn register by 2
1 0: Decrement ADCBn register by 1
1 1: Decrement ADCBn register by 2
asserted.
can only be used for SW DMA requests (i.e., when SWRQ is set). On HW DMA requests, BPC must be set to 0.
(Continued)
Description
93
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