pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 156

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Mode Select Register (UnMDSL)
This byte-wide read/write register controls the selection of the clock source, Synchronous mode, Attention mode and line
break generation. It contains the enable bits for the DMA channels. The register is cleared (00
Location: USART1 - 00 FD2A
Type:
USART1
USART2
Bit
Name
Reset
Bit
Name
Reset
7-6
Bit
0
1
2
3
4
5
MOD. Selects the Synchronous or Asynchronous mode of operation:
0: Asynchronous mode (default)
1: Synchronous mode
ATN. Selects the Attention mode of operation. Cleared by hardware after reception of an address frame that is
a 9-bit character with a ‘1’ in the ninth bit position.
0: Disable Attention mode (default)
1: Enable Attention mode
BRK. Setting the bit (1) causes UTXDn to go low. UTXDn remains low until the bit is cleared (0) by the user.
CKS. Controls the source of the clock while operating in Synchronous mode (MOD=1).
0: USART operates from the baud rate generator and outputs the baud rate clock on USCLKn (default)
1: USART operates from an external clock provided on USCLKn
While the USART is operated in Asynchronous mode (MOD=0), the bit has no effect.
ETD.
0: No DMA request is asserted for transmit operations (default)
1: DMA request is asserted when the Transmit Buffer Empty (TBE) flag is set (1)
ERD.
0: No DMA request is asserted for receive operations (default)
1: DMA request is asserted when the Receive Buffer Full (RBF) flag is set (1)
Reserved.
USART2 - 00 FC2A
R/W
7
0
7
0
Reserved
16
16
6
0
6
0
Reserved
ERD
5
0
5
0
(Continued)
ETD
Description
156
4
0
4
0
CKS
CKS
3
0
3
0
BRK
BRK
2
0
2
0
16
) on reset.
ATN
ATN
1
0
1
0
MOD
MOD
0
0
0
0
Revision 1.2