pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 134

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Mode 3, Dual Independent Timer
Dual Independent Timer mode can be used for a wide variety of system tasks such as the generation of periodic system
interrupts, based either on the prescaled clock or external events on TBn. The timer can also toggle TAn pin on underflow,
allowing the simple generation of a processor-independent 50% duty cycle signal on TAn. In this mode, TnCNT1 counts
down and reloads from TnCRA on underflow while TnCNT2 is reloaded from TnCRB on underflow.
In this mode, the timer is configured to operate as a dual independent system timer or dual external event counter. In addi-
tion, timer/counter 1 can generate a 50% duty cycle signal on the TAn pin. The TBn pin can be used as an external event
input or pulse accumulate input and forms the clock source to either counter 1 or counter 2, as described above. Both
counters can also be operated using the prescaled system clock. Figure 48 shows a block diagram of the timer in mode 3.
Timer/counter 1 (TnCNT1) counts down at the rate of the selected clock (see “Counter Clock Source Select” on page 132
for additional details). On underflow, TnCNT1 is reloaded from TnCRA register and counting proceeds. If enabled, the TAn
pin toggles on underflow of TnCNT1. Software can select the initial value of the TAn output signal as either high or low (see
“Timer I/O Functions” on page 137 for additional details). In addition, the TnAPND interrupt pending flag is set, and a timer
interrupt 1 is generated if TnAIEN bit is set to 1 (see Section 4.7.4 on page 136 for detailed information). Since TAn toggles
on every underflow, a 50% duty cycle PWM signal can be generated on TAn without requiring interaction by the core.
Timer/counter 2 (TnCNT2) counts down at the rate of the selected clock (see “Counter Clock Source Select” on page 132
additional details). On every underflow of TnCNT2, the value contained in TnCRB register is loaded into TnCNT2, and count-
ing proceeds downwards from that value. In addition, the TnDPND interrupt pending flag is set, and a timer interrupt 2 is
generated if TnDIEN bit is set to 1. See Section 4.7.4 on page 136 for detailed information.
Timer1
Timer 2
Clock
Clock
Timer/Counter 1
Timer/Counter 2
TnCNT1
Capture A
Capture B
TnCRA
TnCRB
TnCNT2
Figure 47. Mode 2, Dual Input Capture
(Continued)
Preset
Preset
Underflow
134
Underflow
TAEN
TBEN
TCIEN
TAIEN
TBIEN
TDIEN
TCPND
TAPND
TBPND
TDPND
Interrupt 1
Interrupt 1
Interrupt 1
Interrupt 2
Timer
Timer
Timer
Timer
TBn
TAn
Revision 1.2