pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 293

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Module
MSWC Control Status Register 3 (MSWCTL3)
This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. The contents of
this register is preserved by V
Location: 00 FCC4
Type:
Host Configuration Base Address Low (HCFGBAL)
This is a byte-wide read/write register that holds the lower byte of the Host Configuration Registers base address. Bit 0 of
this register is always forced to 0 to guarantee address alignment. This register is cleared on V
Location: 00 FCC8
Type:
Host Configuration Base Address High (HCFGBAH)
This is a byte-wide read/write register that holds the higher byte of the Host Configuration Registers base address. This reg-
ister is cleared on V
Location: 00 FCCA
Type:
Bit
Name
Reset
Bit
Name
Reset
Bit
Name
Reset
Bit
7-3 Reserved.
0
1
2
HRAPU (Host Reset when Accessed During V
the host if LPC activity was detected while the V
any LPC transaction that may have addressed the PC87591L-N05 but could not be handled correctly. When
HCFGLK bit is set, writes to this bits are ignored.
0: Do not generate a reset on LPC transactions while the PC87591L-N05 is in Power-Up reset
1: Assert KBRST output on LPC transactions while the PC87591L-N05 is executing the V
LPFTO (LPC Power Fail Turn Off KBRST and GA20). Indicates the handling of KBRST and GA20 outputs
when LPCPD is active.
0: Ignore LPCPD in handling these signals (default)
1: Force the two signals low while LPCPD is active or V
RTCAL (RTC Alarm). Indicates that an RTC Alarm event occurred. This bit is set on the rising edge of the RTC
Alarm output. It is cleared by writing 1 to it. Note that the ALARM event detection is edge triggered by the
RTCAL bit; thus for a new event to be detected, first RTCAL bit and then Alarm Status bit in the RTC must be
cleared.
0: No RTC Alarm is flagged (default)
1: RTC Alarm rising edge was detected
R/W
R/W
R/W
quence (default)
16
16
CC
7
0
7
0
7
0
16
Power-Up reset.
PP
and it is reset only on V
6
0
6
0
6
0
Host Configuration Registers Base Address High
Host Configuration Registers Base Address Low
Reserved
5
0
5
0
5
0
(Continued)
PP
CC
CC
Description
Power-Up reset.
293
Power-Up reset was not completed. This intends to re-start
4
0
4
0
4
0
Power-Up Reset). Indicates that a reset should be sent to
DD
is low
3
0
3
0
3
0
RTCAL
2
0
2
0
2
0
CC
Power-Up reset.
CC
LPFTO
Power-Up reset se-
1
0
1
0
1
0
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HRAPU
0
1
0
0
0
0